#### Useful Tools

contact us contact tutor/group email to a friend accessibility options report a fault
Analogue and Mixed Signal IC Design

# Analogue and Mixed Signal Integrated Circuit Design

## Unit 1: Bipolar Transistor Characteristics and Current Source Design

This unit introduces the basics of bipolar transistor theory. Consideration is then given to the design of current sources and mirrors which are used extensively for biasing purposes and as active loads in high gain amplifiers. The subject of amplification itself will be covered in Unit 2. There is a lot of theory in this unit but be reassured that later units contain less theory and more practical circuit applications.

### Key Information

Signal Naming Convention DC or bias levels are universally represented by an upper case letter and subscript, such as IC for the collector current of a bipolar transistor. Similarly, ac or signal quantities are represented by a lower case letter and subscript, ic. Finally there is the total current, which represents the actual value produced by any signal current superimposed on the bias current. I intend to represent this by a lower case letter and upper case subscript, iC. This convention is commonly used in textbooks.

[You should note that it is also possible to represent the total current by the final available combination of letters, Ic. This convention is used in some books, including Gray & Meyer (see p. xiv) but, in my opinion, creates more potential for confusion than the iC form.]

Having established a convention, you might still find me straying from it from time to time; in which case, I hope the meaning is clear from the context but if not please complain to me.

Throughout the module a lower case letter 'u' is used to indicate 'micro'. Hence 100uA = 100 micro Amps. This is consistent with an identical convention used in SPICE simulators.

### 1.1 Characteristics of Bipolar Transistors (BJTs)

#### 1.1.1 Currents

In the active linear region of operation, assuming conventional current flow, IB and IC flow into the transistor, while IE flows out. Transistors can store small amounts of charge but, in general, what flows in must come out. So for the dc bias currents we can write:

IC + IB = IE (1)

And the same relationship applies to the signal currents:

ic + ib = ie

The total collector current, using the convention above, is iC = IC + ic

The dc forward current gain, ß, is defined as IC/IB. ß is also known as hFE but this terminology is less common, now that 'h parameters' have fallen out of general use. The equivalent Spice parameter is BF.
ac current gain can also be defined as ic/ib but the dc and ac values are similar in most cases. One exception is where the maximum current handling capability of the transistor starts to be exceeded. When this happens, an increase in base current will not yield the hoped for increase in collector current and the ac current gain falls.

Substituting for IB into equation (1) gives:

IC + IC/ß = IE, hence IC = [(ß/(1+ß)]IEor IC = a IE         (2)

At room temperature, ß is typically 100 or greater, so a is normally greater than 0.99.

Considering electron flow for a moment, an emitter current is a flow of electrons initially from the emitter to the base induced by a sufficiently positive base-emitter voltage. A few of the electrons suffer 'a misfortune' in the base region, such as combining with a positively charged 'hole', and they don't make it to the collector region, but most of the electrons are swept through the base region to the collector region because of the field produced by the relatively high collector voltage. Those electrons, usually at least 99% of those that set off from the emitter, form the collector current.

When designing, it is not possible to rely on a particular value of ß. One cannot force a certain base current and have any confidence about what the collector and emitter currents will be. The room temperature value of ß can vary over a range of 100 to 500, or even more.

In addition, ß increases strongly as a function of temperature: by as much as +7000 ppm/° C according to Gray and Meyer, p28.

Warning: ß can drop to very low levels at -55° C. Design of any circuits intended for this extreme temperature range must take this possibility into account. Although the chip temperature will be elevated after a time due to internal power dissipation, this is not the case when the device first turns on and it has to be able to operate reliably assuming a worst case scenario.

Implications of finite ß

• A BJT always needs a dc bias current into the base.
• Similarly, when a signal is applied, there is always a signal current into the base, which determines the dynamic ac input resistance of the device.
• In a BJT, the base and collector-emitter circuits are not isolated from each other.

Design Hint

In many cases, circuits can be designed assuming infinite ß, but later by means of calculation and simulation the effects of finite ß must be taken into account and, where possible, compensated for.

#### 1.1.2 The BJT as an Amplification Device

The performance of a BJT is often represented graphically as a family of curves of IC as a function of VCE, for different values of base current. The following example is taken from unit 3.4 of module AMI4005.

In practice, curves such as these are not very helpful and traditional graphical solutions based on load lines are unenlightening. A more useful approach relies on the fact that base current is a function of vBE. From this it is possible to obtain the following equation which relates collector current to base-emitter voltage directly.

iC = ISexp(vBE/VT)             (3)

In the above equation, VT is equal to kT/q, where k is Boltzmann's constant, q is the charge on the electron and T is absolute temperature in degrees Kelvin.

VT evaluates to approximately 26mV at 300° K.

Study of equation (3) might suggest that collector current would reduce with increasing temperature. This is not the case because IS itself increases rapidly with temperature.

From a design point of view, the important idea is that at a fixed temperature and for a particular transistor, IS can be regarded as a constant. The practical application of this idea is that when two nominally identical transistors are adjacent to one another on the same chip they will have experienced the same manufacturing process and they will be at the same temperature. It can therefore be assumed that under such conditions, the IS values for the two devices will be very closely matched.

Consideration of equation (3) shows that for the same applied vBE, two ideally matched transistors will have the same collector current.

Although constant under certain conditions, IS is still an unknown quantity. In particular it is not possible to look up this value in a data sheet. Therefore equation (3) doesn't allow us to predict the exact value of iC that will be produced by a given value of vBE. For this reason, BJTs are never biased by applying a fixed base-emitter voltage because the collector current produced would be initially unknown and would vary wildly with temperature. It is nonetheless still possible to derive two useful relationships from equation (3).

Small Signal Behaviour and Transconductance (gm)

gm is defined as diC/dvBE.

Differentiating equation (3) gives

gm = diC/dvBE = (1/VT) ISexp(vBE/VT) = IC/VT (4)

Notice that, because we can choose to bias the transistor at a particular IC value, we do not need to know the exact value of the otherwise problematical parameter, IS.

Output Resistance and Early Voltage

Current Gain (b or BF) increases as VCE increases. This means that the output resistance of a BJT is finite. Consider the 'flat' lines on the IC v. VCE characteristic and extrapolate them to the left until they meet the (negative) VCE axis. They will all meet the VCE axis at the same negative voltage. This voltage (with the negative sign omitted) is known as the Early Voltage for the transistor represented by the SPICE parameter VAF.

Equation (3) can be re-written:

iC = ISexp(vBE/VT) [1 + VCE/VAF]

The small signal output resistance of the device, ro = VAF/IC

Input Resistance

rin is defined as dvbe/dib = dvbe/(dic/b ) = b /(dvbe/dic) = b/gm

### Self Assessment Questions

Attempt Questions 1 - 3

#### 1.1.3 Large Signal Behaviour

It is useful to be able to calculate the change in iC that is produced by a change in vBE.

Equation (3) can be re-arranged in terms of vBE.

vBE = VTln(iC/IS)         (5)

Now imagine two identical transistors operating at different collector currents, iC1 and iC2.

vBE1 = VTln(iC1/IS) and vBE2 = VTln(iC2/IS) so the difference in vBE values is

D vBE = vBE1 - vBE2 = VT[ln(iC1/IS) - ln(iC2/IS)] = VT ln(iC1/iC2)(6)

Alternatively, D vBE = 2.3VT log(iC1/iC2) (7)

Notice that, once again, the value of IS is cancelled and does not affect this relationship.

Transistor Area

Consider the following diagram:

In view of what we have said about ideally matched transistors taking the same current when under the same bias conditions, it follows that IC2 will be twice IC1.

This property of analogue integrated circuits allows currents to be scaled up (or down) simply by using the required number of transistors. In layout terms, one approach to this is to place the required number of transistors side by side, but there is an alternative. Current conduction, for a given applied base-emitter voltage, is really determined by the size (area) of the emitter. Thus the double transistor shown in the diagram could be achieved by placing two identical emitters within one transistor. As well as saving space on the chip, this approach will also reduce collector-base capacitance.

Normally the semiconductor process will determine the minimum reproducible emitter area that will give acceptable matching. All transistors are then scaled-up versions of this transistor with n emitters where n can of course be one.

Equation (3) can now be generalised and re-written as follows:

iC = A.ISexp(vBE/VT)         (8)

where IS is the saturation current of a single emitter transistor and A is n, the number of emitters.

You may like to satisfy yourself that this refinement has no affect on gm. It is still as given in equation 4.

Equation (6) can be re-written as follows:

D vBE = vBE1 - vBE2 = VT[ln(iC1/A1IS) - ln(iC2/A2IS)] = VT ln[(iC1/A1)/(iC2/A2)](7)

where A1 represents the number of emitters (or the effective area) of transistor 1 etc.

Equation 7 shows that the relative base-emitter voltages of two transistors are determined by the ratio of their currents divided by their areas, also know as 'current density', J. The current density version of equation 7 is shown below:

D vBE = VT ln[J1/J2]   (8)

Note that it is possible to vary the AREA parameter within SPICE. With AREA set to 2, say, the simulation is carried out exactly as if two transistors are wired in parallel. For example all capacitances are doubled and so is the maximum current handling of the combined transistor. Having multiplied certain parameters by two, SPICE handles the combined transistor as a single device, which simplifies the simulation task.

### Self Assessment Questions

Attempt Question 4

### Exercise

Try different values in the two Bipolar transistor calculators.

### 1.2 Design of Current Sources

#### 1.2.1 Introduction

Current sources have two main applications in analogue design:

• Biasing
By definition, a current source will supply a constant current irrespective of the magnitude and frequency of the applied voltage.

A BJT is itself a voltage controlled current source. Practical current sources have a number of limitations, some of which are shown in Figure 2, above.

1. Static errors - the current produced may not be as desired.
2. Dynamic errors - the current may vary as the applied voltage changes. Note in Figure 2 how IC changes as a function of VCE because of the Early effect.
3. Voltage compliance limit - in Figure 2, it is clear that the correct current will not be maintained for low values of VCE.
4. High Frequency errors - current sources are active circuits with internal feedback paths and their performance will degrade at 'high' frequencies. This aspect of performance can only be determined by simulation.

#### 1.2.2 A Simple Two-Transistor Current Source

The following diagram (see also Figure 4.1 from Gray and Meyer) represents one of the simplest possible current sources and is also known as a 'current mirror' because the current into Q1 is (hopefully) mirrored to become the output of Q2.

Note: Because the output current flows into Q2, rather than out of it, this circuit is strictly a current sink and not a source; but the term 'current source' is normally used nonetheless. It should also be pointed out that the output current can easily be scaled up by, for example, doubling the area of Q2. The output current would then be very approximately twice IREF.

There is a considerable static error because IOUT does not match IREF. The collector of Q1 is tied to its base so the collector voltage will be around 0.7V. If the collector of Q2 is held at the same voltage then (assuming perfect matching) the two collector currents are identical. Unfortunately IC(Q1) is not IREF but (IREF - 2IB). If BF is as low as 100, this can lead to a 2% static error.

Dynamic errors can be even more significant due to the Early effect described above. Early voltage varies depending on the technology used but, as an example, 20V Early voltage will result in a 5% change in IOUT for a 1V change in the applied output voltage.

The final low frequency consideration is that the current source will only work with a voltage that is below the breakdown voltage. Again this is technology dependent. Neither can the current source operate with 0V on its output. A practical minimum is between 100mV and 200mV but this is as good as you can get with a BJT.

More complex current source designs are aimed at improving either static and/or dynamic accuracy but this is often at the cost of providing a much worse minimum output voltage. Additional diodes are often involved which will raise the minimum voltage typically to 800mV.

#### 1.2.3 Enhanced Current Sources

The following current sources aim to tackle the problems of errors due to finite beta and low output resistance.

Simple Current Source with Current Gain (see G&M Figure 4.4)

The base current error inherent in the operation of the simple mirror is solved by an additional transistor that supplies the base currents to Q1 and Q2.

Cascode Current Source

Output resistance can be increased greatly by placing a 'cascode' transistor in series with the output of Q2.

The story goes that Barrie Gilbert had an informal contest with one George Wilson to see who could come up with the most useful three-transistor current source. George Wilson won and gave his name to this elegant and very effective design. 'As if by magic' the base current errors associated with the two-transistor source are almost completely cancelled out and the additional transistor has the very desirable effect of greatly increasing dynamic output resistance. IOUT is almost exactly equal to IREF but it is not possible to adjust the design to make IOUT a multiple of IREF. The minimum output compliance voltage is approximately 800mV.

Hand calculation of this circuit is surprisingly difficult but if you assume the result (IOUT = IREF) you should be able to see how the base current errors of the two-transistor mirror are cancelled.

Emitter Degeneration

This technique addresses the output resistance problem by placing 'feedback' resistors in series with the emitters.

Simply put, the argument runs that if Q2's collector current should rise, the resistor voltage, which is Q2's emitter voltage, will rise and tend to turn Q2 off again. From a qualitative viewpoint this is all very well but the obvious question is, "Just how effective is this idea?"

It turns out that Q2 now operates with an apparently greatly improved Early voltage:

VAF(effective) = VAF(1+VRE/VT)

Another advantage of this technique is that the current mirror ratio depends not just on transistor matching but also on the matching of the two RE resistors. The overall matching obtained is usually better than you would get from two transistors alone.

This current mirror only works well for that narrow range of currents which derives the correct voltage across the RE resistors. At low currents, RE will have no effect; at higher currents, the minimum output compliance voltage will be raised unacceptably.

### Self Assessment Questions

Attempt Question 5

The Widlar Current Source

In this current source, attributed to the late Bob Widlar, the emitter degeneration resistor, RE is only applied to Q2. This has the effect of turning off Q2 relative to Q1. The current source is commonly used to generate low currents.

D VBE = VRE = VTln(IC1/IC2) = IC2 x RE

Knowing the desired values of IC1 and IC2, RE can be easily calculated.

### Self Assessment Questions

Attempt Question 6

### WWW Research

The late Bob Widlar was a giant in the world of analogue design. I have been unable to find any substantial web links about him but this is the best I have found. "Horrible" refers to a photograph.

http://www.national.com/rap/Horrible/widlar.html

Barrie Gilbert is very much alive. The link below serves two purposes. First there is a provocative article about the role of BJT technology in current and future analogue design practice and at the end of the article there is a succinct profile of the man which clearly conveys his outstanding contribution in this field.

http://www.edtn.com/analog/barrie2.htm

### Further Study

The material in this unit is expanded upon in G&M Unit 1.3 and 1.4 and Unit 4.