Online Postgraduate Courses for the Electronics Industry

Provided By The University of Bolton

• Home
• About Us
• Questions & Answers
• Courses
• Students
• Links

Useful Tools

Business Issues of Microelectronics

Unit 2: Integrated Circuit Processing

Contents

• 2.1 Classes of Product
• 2.2 Semiconductor Processes
• 2.3 Wafer Fabrication
• 2.4 Process Validation
  • 2.4.1 Process Yields
  • 2.4.2 Wafer Testing, Die Separation and Assembly
• 2.5 Multi project wafer/split-batch services
• 2.6 Further Reading
• Self Assessment Questions

Notional workload: 5 hours

2.1 Classes of Product

There are two broad classes of IC product - merchant parts and application specific ICs - ASICs. The latter are specific to the organisation which paid for their development and cannot be used by anyone else.The former are made to a declared public specification which is not related to any user's system. It is non-negotiable except possibly to major users. Others must take it or leave it.

Merchant parts are made in large volumes and are able to be sold at competitive prices.

ASICs are often required in small volumes and are usually more expensive to buy (though they may still be competitive). The reason is that for many ASICs the volumes are too 'small' to reduce the fixed cost contribution to a low level compared with the variable cost.

The price of a merchant part is fixed before release and based on anticipated volumes. It is structured in various price breaks against number of parts procured, with high volumes being well discounted.

ASICs, on the other hand are subject to individual quotation for a specified volume or volumes.

[Back to Top]

2.2. Semiconductor Processes

Merchant parts and ASICs use the same semiconductor processes.

They take a start material which is usually ultra-pure silicon and convert it, in a series of steps, into integrated circuit chip (also known as dice).

The base material for silicon is a sand.  The sand is melted and refined to a high level of purity.

An ingot is drawn from molten pure silicon in a crucible. This ingot starts by dipping a seed crystal in the melt and pulling it back at a controlled speed and temperature profile.

The resulting cylindrical ingot has the single crystal structure required to manufacture active devices.

Ingot Pulling

After cooling, the ingots are sawn, normal to the cylinder axis, into disks, typically 500 microns thick.

These disks or 'wafers' are the basic start material for microelectronic device fabrication.

From this point three classes of process are involved - patterning, diffusion and deposition.

[Back to Top]

2.3 Wafer Fabrication

The basic wafers are intrinsic semi-conducting material.

They require the local addition of doping atoms to create semi-conducting devices.

The dopants are introduced by the diffusion process.

The wafers are uniformly coated with a thin layer (usually) of silicon dioxide which is itself coated with a photoresist and exposed through a mask to the appropriate sensitising radiation.

Themask is usually made from an optically flat plate of dimensionally stable borosilicate glass, one side of which is coated with a fine coat of material (typically chromium) that is opaque to the sensitising radiation.

After exposure the resist is washed away to bare the surface of the silicon dioxide.

Etching the silicon dixide now exposes those areas of the wafer beneath it that are to receive a dopant in a diffusion step.

Batches of exposed wafers are mounted vertically in a carrier (commonly called a boat), and passed through a diffusion furnace (typically at 1,100ºC) containing a gaseous atmosphere of the element to be diffused (e.g. phosphorus).

Loaded Boat

Furnace (Thermco Systems)

The duration of the wafer exposure determines how deeply the diffusion penetrates the wafer.

During the first diffusion step the oxide is stripped from the wafer and a fresh layer is grown for the succeeding step so that the process can be repeated for the successive impurity diffusions needed to build up all the circuit elements required in the die.
When all the diffusion steps are complete, the devices in the die have to be interconnected.

This is effected in a series of metal deposition and etch steps.

The diffusions usually leave the wafer covered in silicon dioxide. Resist is applied, irradiated and washed to expose the locations of the contact points in the components diffused in the wafer.

There are a number of diffusion steps and their associated masks.

The number ranges between five and eighteen or more.

The first etch step removes the insulator covering the contact points. The first deposition puts a thin layer of interconnect metal, usually an aluminium alloy, over the whole wafer and into the contact areas exposed on the silicon.

The second etch removes the unwanted aluminium to leave only the interconnect tracks and substrate contact pads. 

Two or more layers of metal may be required for complex interconnect. Polysilicon layers may also be used - for instance to make capacitors which must be isolated from the die substrate.
Automated Acid Etch (SEZ)

A typical figure for CMOS is eight or nine with a further two for single layer metal and two more for every additional layer.

Electron-beam exposure of a special resist is occasionally used to define very small features. It is used in several ways.

One of its distinguishing characteristics is that each mask has to be written individually.

A second is that each die in the mask has to be written individually whereas conventional photolithography can use a single master for the chip to be manufactured and expose it to the wafer in a 'step-and-repeat' process which forces all the die to be identical.

These characteristics have advantages and disadvantages.

E-beam written masks are expensive.

It is often cheaper to make one e-beam mask and to take a chrome on glass mask plate from it rather than to direct write more than a single wafer.

Since each die is written individually, each one can be different - unwise from the point of view of yield - but feasible.  More usually, masks are made or a wafer is written with a number of different designs - either repeated in groups or repeated in blocks of the same design.  These are known as multi-project wafers.

• They are used for low cost fabrication of small numbers of dice.
• These may be for prototyping or for low volume production.
• Production parts usually carry a price premium.

The low cost feature derives from the sharing of the fabrication costs between a number of users.  Multi-project Wafer (MPW) principles can be used for cell based and custom ASICs. The technique is useful whenever the validity of the design is uncertain.

• It shows time and cost savings if the design has to be modified as a result of prototype tests.
• It results in costs and time penalties if no modification is needed.It is therefore an insurance against that risk that has to be weighed against its cost in time and funding. The same considerations apply to all three types of ASIC.

Access is usually at defined intervals and is charged in proportion to chip area.

The frequency of access depends on demand, so popular processes are available more often than the more specialist processes.

MPW is a cheap rather than a fast route to prototypes.

[Back to Top]

2.4 Process Validation

A wafer may hold tens of large, complex dice or thousands of small ones in a grid of small rectangular areas.

A number of test circuits are also built into the wafer. They may be as few as two in small wafers and many more in large ones.

They are designed to monitor the quality of the diffusion and deposition steps and the inter-layer mask registration errors.

Known as 'test inserts' or 'step-in' these test circuits also act as the contractual determinant of whether the wafer is deliverable as conforming to the design and performance limits specified by the manufacturer. This applies regardless of the performance of the die within it. If they don't work you still pay - and redesign the chip.

A typical wafer-yield rate at this point is 80%-95%.

2.4.1 Process Yields

A wafer may hold tens of large dice or thousands of small ones. The limiting factor is yield.

The wafers are monocrystalline but contain lattice defects distributed thinly throughout them.

These defects cause transistor malfunction.

Every wafer contains a number of such defects and defect density is one of the specified parameters in wafer procurement.

As a result of these defects each wafer contains a number of randomly distributed chips which malfunction and must be scrapped.

Average yields are carefully monitored by the foundries as a further check on wafer quality and consistency.

The start material of the wafers has a defined defect density that processing adds to. On average about one in three defects causes a chip to malfunction. As the number of defects increases with chip area the chip yield falls and the cost per die increases. So there is an economic limit to die size, and hence complexity, set by the cost per yielded die.

If the dies are made larger than a certain size it becomes statistically possible that every one of them will contain a defect and that yield will be zero.

So there is an economic limit to die size (and hence circuit complexity) set by the quality (and costs!) of the basic wafers.

2.4.2 Wafer Testing, Die Separation and Assembly

The first step on receipt of a batch of wafers is to test them.

The wafers will be supplied with a copy of the results from the manufacturer's measurements on the test inserts.

The first action on receipt if you do not have a good user/supplier history is to repeat these tests and verify the results.

The wafer testing is fully automatic with the wafer held in a carrier.

The individual chips are positioned in sequence under a test fixture having probe pins to contact each pad round the chip periphery. A different fixture is used for each chip type.
The wafer carrier is mounted in a precision machine controlled X-Y table. Position errors in the location of the wafer are zeroed-out before starting test.

During test, each die in turn is presented to the test probes and subjected to test waveforms generated by a test program.

Dies failing to pass the test are marked - usually by an ink blob on the die surface.

On completion of the tests the wafer carrier is removed from the tester and passed for the die saw and die sort operations.

Sawing of the die is done automatically.

The dies are separated on the wafer by narrow blank strips of silicon known as scribe channels - a throw-back to the days when the dies were separated by scoring and breaking the wafer in the same way as window glass is cut to size.

Currently the dies are separated by sawing the wafer with a diamond tipped saw 25 or less microns thick.

The wafers are sawn on an automatically controlled table which translates the wafer under the saw blade.

The table is stepped sideways by one scribe channel pitch after each traverse. The table rotates through 90 degrees when all the scribe channels have been cut in one axis.

The process is then repeated to completely saw the wafer. The process is fully automatic once the scribe channel widths have been entered and the wafer and saw have been aligned.

The saw is usually set to cut just short of breaking out on the underside of the 500 micron thick wafer. The precision of all these operations is extremely high.

Die separation is by flexing the wafer on its support so that it cleaves cleanly along the saw lines.
This method produces a cleaner break than allowing the saw to break through the wafer.

However, there is inevitably some damage caused by sawing and a resulting yield loss.

This loss is determined by the total length sawn and increases rapidly as the chip size reduces.

There is therefore an increasing yield loss which is significant below a given chip size.

This is followed by attaching the die to its package ( or its assembly header for plastic encapsulation), inspecting the attachment and bonding the lead out wires between chip and package pins.  They are then inspected and the package sealed in an inert atmosphere such as dry nitrogen and leak tested.  The finished part is then tested.  Refer to Text for Module mdesign hypertext link.

There are two types of wire bond:  gold ball bonds (as shown in the photo) and wedge bonds which are usual with aluminium wire.

Manufacturers might, at some time, be forced to accept a lower yield than is desirable and suffer the cost penalty. Examples of such possible situations are:

• they have committed to a new process and the yields have not stabilised but early models are needed urgently.
• when the best process available is approaching the limits of economic die size at the complexity of the design.

The next step following die separation is sorting and inspecting the unmarked die from the wafer and preparing them for assembly in packages.

There may be further quality testing or operations such as burn-in, accelerated life tests, functional tests at high and low temperature depending on specific customer requirements. Devices destined for travel in space and implanted medical devices carry extremely heavy cost penalties for failure.

[Back to Top]

2.5 Multi project wafer/split-batch services.

Some foundries run a multi-project wafer service (MPW).

This arranges several different die types on the same mask so that they can be processed simultaneously.

The total costs are shared, usually in proportion to the wafer area used.

This enables a small number of parts to be obtained at lower costs than a full fabrication run which normally involves a minimum of one e-beam mask and two wafers for a mask - programmed device and twelve wafers for a custom or cell-based device.

The MPW approach can be employed for very small volume production but it is more usually used for prototyping.

It is an approach which will reduce cost and timescale if a design is flawed and must be iterated but will increase them if  its justification is risk reduction rather than cost reduction.
A split batch arrangement can sometimes be employed, for the same reason, on a full mask set (cell-based and custom) ASIC.

In its simplest form the full boat of wafers is put through diffusion but only part of it is metallised - usually a half. (This is where the batch splits). Prototype parts are assembled from the completed half batch and supplied for evaluation.

This service is appropriate where there is some uncertainty about a specific design feature and where mask programmed interconnect changes can be used to optimise that feature. The first half batch is used to determine (or confirm) the correct interconnect configuration. The second half batch is then programmed with the changes.

There is at present one source which will process a batch wafer by wafer.

A typical gate array MPW service operates along the following lines.

• It will be priced to break even on a particular number of designs per run - say five, and will operate to a fixed regular schedule - eg. designs will be accepted up to mid-day on the first Tuesday in the month (avoiding Bank Holidays).
  
  
• It will accept netlist and test vector data together with confirmation of simulation of the netlisted functions to a defined requirement of the service.
  
  
• On receipt of the netlist the service places the cells, routes the interconnect and runs a post-layout simulation including the interconnect parasitics.
  
• The various designs are then consolidated into blocks and mask data produced.
  
  
• This data is then submitted for fabrication. These steps typically take one week.
  
  
• An e-beam master is then written, a mask produced and two wafers are etched (two in case of any problem that might disable a single wafer).
  
  
• They are parametrically tested, sawn and packaged. It is usual to ship parts untested and to accept slightly lower yield.
  
  
• If the array is one of a family, all MPW designs will be fabricated on the biggest array in the family regardless of their complexity.
  
  
• All prototypes will be assembled in a single package type and with a common bonding diagram.
  
  
• The whole batch is then processed with only one set of assembly paperwork per run. This procedure keeps costs low.
  
  
• Manufacturers are required to carry out whatever tests that are needed to assess the prototypes.
  
  
• There then follows a 'productionisation' phase with the foundry - independently of the MPW service. This generates the production layout on the actual target array (if different from the array used for prototyping), the production test program from the original test vectors and any jigs and fixtures needed for production.
  
  
• Typical timescales are:
  • Closure of the run to shipping mask data - 1 week
  • Foundry processing and shipment - 2 weeks
  • Test assembly of prototypes and shipping - 1 week
  • Total elapsed time - 4 weeks

The elapsed time between acceptance of the prototypes and receipt of the first batch of production parts is typically eight weeks.

The total elapsed time is therefore twelve weeks plus the time required for prototype approval.

The timescale for submission to the foundry of a single design is slightly shorter as the design is targetted into the final array size and package from the outset. It is slightly faster if no design change is needed - but several times more expensive.

Some routes may offer an accelerated route at additional cost.In this arrangement the data required for fabrication is delivered to the foundry by hand - seen through fabrication and hand carried back.

It is an arrangement which requires close liaison between design and the fabrication organisations.

MPW procedures for cell-based and custom designs are more complex and expensive because there is no common die size, a full set of masks has to be made and a full process run is required.

Typical turn round times are three months compared with the four week gate array turn round. The price of a run is usually fixed by die area.

[Back to Top]

[Back to Top]

Site Search

Powered by Google
Site Map