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Business Issues of Microelectronics

Unit 3: Device Types

Contents

• 3.1 Device Types
• 3.1.1 Circuit Structures 
• 3.1.2 Asic Devices 
• 3.2 Programmable Devices
• 3.3 Review of Devices
• 3.4 Web Sites of Interest 
• Self Assessment Questions

Notional workload: 5 hours

Objectives : To understand the cost benefits and relative competitive advantages of various types of IC Device Families.

3.1 Device Types

3.1.1 Circuit Structures

There are two basic types of integrated circuit structure. In the first, the custom ASIC, the chip is like a PCB with discrete components spread all over it - usually over as small a total area as possible. In the second type of structure an array of identical devices forms a regular pattern with spaces left for their interconnection.

A typical Printed Circuit Board

The components can be interconnected in different ways to create different individual functions. The functions most commonly found are digital logic gates (in a device known as a 'gate array') but they can also be discrete circuit components including various types of transistors, diodes (including Zeners), resistors, capacitors, etc. These component arrays can be interconnected by mask programming of the metallisation to execute a particular collection of functions - usually analogue. Standard gate array components can also be interconnected to execute analogue functions but the performance is not very good. However it is sometimes an effective way of integrating limited analogue functionality with mainly logic functions.

The key feature of these array devices is that all the wafers contain the same expensive diffusion layers. Their individual customisation only involves the lower cost 'deposit and etch' processes - and frequently in only one layer. The base wafers are therefore fabricated in the high volumes needed to meet the totality of wafer demand. These fixed costs are reduced, in proportion, to a low level per wafer leaving design as the primary non-recurring fixed cost. This now permits a cost structure better suited to lower volumes and priced between the merchant part and the custom ASIC.

Merchant parts sell into high volume, competitive wide-application markets. They can therefore carry a high development cost. Part of this cost goes into tuning a process line to a particular requirement. For instance it could be ADCs requiring a wide dynamic range, low input noise and stable, low offsets.

Companies such as Analogue Devices have leading positions in this product area. They sustain it by generating new product after new product (often derivatives of existing products) in order to stay ahead of their competition. They also exhibit market segmentation - so Analogue Devices produce a range of selected functions and ignore others. These strategies of replication and segmentation - as mentioned earlier - give them commanding positions in high value niche markets of products.

3.1.2 Asic Devices

So far we have looked at custom ASICs and arrays. The 'array' devices are essentially general purpose and will accommodate a range of design complexity. However, the circuit utilisation is generally limited by the amount and flexibility of the interconnect provided. An economic limit would normally be about 75% gate utilisation. It can be increased but at the expense of additional design costs - usually steeply increasing costs. It follows that, with 75% utilisation, the cost per unit area is increased by at least one third and an average of 60%. Arrays are normally available in 'families' of different sizes.The typical area ratio between a circuit which just fails to fit the next lower size is about 80%. When compounded with the 75% the step is 60%.

Arrays are available in various processes - CMOS, BiCMOS, SoI (Silicon on Insulator) and GaAs for example. The high complexity arrays have three or four layers of interconnect.

The full custom ASIC is designed almost component by component in a fashion analogous to laying out discrete components on a PCB. Fabrication also involves the diffusion steps as well as the interconnect steps. So a full set of masks has to be made as well as individual designs of each component and the entire interconnect pattern. These devices have the highest NRE costs of all the ASIC devices. Their essential characteristic is that they allow the highest space utilisation possible on the silicon die. This is the ultimate cost-determining factor when volume has reduced the fixed cost contribution to well below the variable costs.

The main limitation on the use of custom ASICs at lower volumes is their very high design costs.These confine low volume use of custom ASICs to applications which are not cost sensitive or where there are offsetting savings. Space applications require high reliability, low weight and low volume combined, in some cases, with specialist processes. In this, and other applications similar in character, cost is not the primary concern and a custom ASIC may be the correct technology to use in spite of its high cost in lower volumes.

In another case the response time of a moving member of a machine was critical. It was improved by using a full custom ASIC on the arm instead of discrete parts. The weight saving gave an improvement in performance which was worth far more in sales than the cost of the ASIC development.

The design costs are reduced in cell-based ASICs which have features common both to full custom and array based devices. Cell-based ASICs have a lower design costs than an ASIC and a larger silicon area. These two parameters lie between those for array and custom ASICs.

The structure of a cell-based ASIC is similar to an array in that it uses a library of functional cells, like the cells in a gate array. They are all designed to fit into rectangles in which one dimension (conventionally the height) is common to all cells. They can therefore be stacked in rows in the same way as the cells in a gate array. However, the interconnections are individually designed for each new ASIC and the chip area devoted to interconnect is reduced to a minimum.This approach uses less silicon than an array and costs less to design than a custom ASIC because of its library of re-useable cells, but the fabrication NREs still involve a complete new mask set, the same as for the custom ASIC .Its field of application lies in volumes between those appropriate to arrays and those appropriate to custom ASICs.

Graph 1 - Cost versus parts volume

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3.2 Programmable Devices

There are three further classes of device to consider. All are programmable merchant parts. The first is Field Programmable Gate Array (FPGA) and logic devices. The second is field programmable analogue/mixed signal devices and the third is the microcontroller.

EPLDs and similar logic devices have limited fields of application. There is currently only one source of programmable mixed signal functions. It is essentially a front end for a microcontroller/microprocessor with a degree of reconfigurability. However, more parts of this general type can be expected to appear.

There is an essential difference between ASICs, the FPGA and microcontroller. The last is software programmable. The FPGA (like the mask programmed array) is programmed by its interconnections.In the mask programmed array the metallisation first covers the whole wafer and is processed to eliminate the unwanted connections. One type of FPGA uses a similar process. All possible interconnect paths are closed through fusible links which can be 'blown' be applying 'high' voltage to them. This approach leaves only the connections required to be made. A second type of arrangement is provided by an 'antifuse' which makes the connections required. In a third variety the contacts are made through analogue switches. The switches are held on by latches which have to be set to programme the device.

The antifuse and fusible links can only be programmed once. They are often called OTP (One Time Programmable) devices. The switch latches have to be reset each time the FPGA is powered up. So this type of device needs a PROM to hold its configuration data. The arrangement has one significant (but little used) characteristic. It is feasible to time-share functions by sequential and rapid reprogramming of the latches and make one device operate several time-shared functions.

Some suppliers will provide mask-programmed versions of proven FPGAs. This allows the initial design investment to be extended to higher volume, without change. It leads to further erosion of the gate array market.

The FPGA has other attractive features. It is possible to purchase programming equipment at low cost. Complete emulation systems are also available. These allow complete functional check of the FPGA design to be run. The total cost is of the order of £2,000.

The design limitation on the FPGA is the interconnect. Increased device complexity depends on using the leading-edge processes in order to obtain high resolution interconnect. FPGAs have therefore tended to increase in complexity and speed rather than to reduce in cost at the same size as was originally expected. All the same, they have taken over completely the small volume/digital logic applications from digital gate arrays. The devices themselves, although produced in higher volumes, are expensive because of the processes they use and the silicon area consumed by interconnect. There is, therefore a point at which the gate array is still competitive. It is determined by volume and complexity.

The microcontroller is a software programmable device produced in very high volumes. However, it is fundamentally different from the others in employing software. This entrains features (in its favour and opposing it) which none of the other devices possess. For this reason parts cost is not the sole determinant in selecting a microcontroller solution to a design problem.

The devices available cover a wide range of capability. Some are self-contained. They can include memory and interface provisions that require only the minimum of external components. Others require additional memory and support chips such as ADCs/DACs and multiplexers.

They are applicable to all kinds of problem but particularly to algorithmically structured ones. Like the FPGA, some suppliers' products can be supplied with mask programmed PROM for higher volume applications. Some, but by no means all, require complex support chips but the majority of microcontroller-based systems are simple.

The devices are straightforward to program using either assembler or compilers such as 'C'.  Most suppliers also hold large libraries of standard, widely used functions - e.g. RS232 interface. You will also build up your own library of re-usable routines. Most suppliers have a range of microcontrollers of increasing capability. The software is almost invariably upwards compatible so it is a permanent investment which may be recovered many times over.

Emulation and checking can be exhaustive and give valuable risk reduction. An additional consequential gain is the necessary imposition of formal procedures for design documentation and change control.  

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3.3 Review of Devices

There is a range of possible microelectronic devices to choose from, each of which is economically viable at different volumes. Novices often tend to think in terms of a single device type for a particular application. This is rarely the case in practice. It is partly so because no one device is universally applicable and because there are other issues than cost to consider. Most requirements are met by a selection of devices such as a microcontroller plus an ASIC plus discrete parts including merchant semiconductor devices.

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