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Microelectronic Design

Unit 1 - Integrated Circuit Design Process

Unit Overview

This unit gives an overview of the integrated circuit design process including the Design, Fabrication and Architectures. Each aspect will then be developed in more detail in subsequent units

Unit Contents

• 1.1 Introduction
• 1.2 WWW Research
• 1.3 The Design Process
• 1.4 WWW Research
• 1.5 Design Considerations - Technology
  • 1.5.1 Silicon
  • 1.5.2 Gallium Arsenide
• 1.6 Design Considerations - Architecture
  • 1.6.1 PLDs
  • 1.6.2 Gate Arrays
  • 1.6.3 FPGA
  • 1.6.4 Standard Cell (CBIC)
  • 1.6.5 Full Custom
• 1.7 WWW Research
• 1.8 Other Design Considerations
• 1.9 WWW Research
• 1.10 Self Assessment Questions

1.1 Introduction

An integrated circuit (IC) is a piece of semiconductor material, most commonly silicon and often referred to as a chip.

Circuit components are built into and on one face (monolithic) and inter-connected by metal tracts to form a complex electrical circuit.

Key features are small size, high complexity, low cost and very high reliability.

Penalties are limited range of component values available, unwanted interactions caused by close proximity of circuit components on the same chip, power dissipation

The IC designer's role is to achieve the required circuit functionality despite IC limitations due to unwanted interactions

• First ICs developed in 1958 by Jack Kilby of  Texas Instruments.
• Development of IC a result of the development of the first transistor by Shockley, Bardeen and Brattain at Bell Laboratories in 1947.
• Initial ICs consisted of only a few transistors and resistors but offered advantages on systems, based on thermionic values, used in computers at that time in terms of reduced size, improved reliability and reduced power.
• Technological improvements now enable chips to be designed containing up to 10 million transistors referred to as Very Large Scale Integration (VLSI).

Scale of increase of complexity (number of transistors on a chip) often expressed as complexity doubles every 2.2 years (Moore's Law) - shown diagrammatically over 50 years from 1960 in Graph 1. Some recent evidence that the increase in complexity is slowing down becoming more of a curve than a straight line (see graph 1). Nevertheless the best estimates are that IC's will contain over 100M components by 2006 and up to a billion by 2010 or so.

Graph 1 - Integrated circuit complexity versus time

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1.3 The Design Process

Design of a complex VLSI chip is a major task - can take many man-years. Teams of designers working on different parts of a chip use Computer Aided Design (CAD) tools to reduce design time and with the objective of ensuring that design is correct first time.

Diagram 1. shows the IC design/manufacturing process overall.  

Figure 1.3 The IC design process

Note: This is a key diagram and the different contributions will be covered in the modules taken on this course and will enable delegates to carry out actual IC designs as they progress through the modules and carry out the final project.

Chip specification drawn up by the system user/designer covering all aspects including functionality, frequency of operation (speed), power dissipation, package type, number of package pins, volume, reliability, voltage and current ratings, etc. Initial specification leads the designer to conclusions on the technology and architecture to be used.

System design and system partitioning into sub-systems follows.

System test considerations taken into account to ensure adequate and economic testing possible. (Design for Test or DFT).

Sub-system design using pre-defined circuits (cells) or specially designed sub-systems if required and allowed within the design style adopted. Often pre-defined cells are used - referred to as intellectual property (IP).

Designs are usually now carried out using a Hardware Description Language (HDL) such as VHDL (Very High Speed IC HDL) for digital systems or Analogue HDL for analogue or mixed analogue/digital systems. Advantage is ease of use, and correct-by-design facility by using a synthesis tool to generate the low-level designs. Traditional design procedure (Diagram 1) is:

• Draw the circuit using a schematic capture package.
• Simulate the circuit using a simulator tool (logic system for digital, circuit for analogue).
• Lay out the chip using a layout package.
• Back-annotate the layout to check for errors and re-simulate using actual layout parameters.
• Mask production from the layout.
• Silicon fabrication using the masks and thin slices of silicon (wafers), test the wafers and package the chips.
• Production test.

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1.5 Design Considerations - Technology

Two materials used for fabricating ICs:

• Silicon (Si).
• Gallium arsenide (GaAs).

1.5.1 Silicon

• Two main types of technologies available in silicon based on Bipolar Junction Transistor (BJT) and Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
• Bipolar technology offers high speed, high current drive but at the expense of high power dissipation, low complexity. It uses n-p-n and p-n-p BJTs, diodes and resistors and is good for analogue and digital circuits.
• MOSFET technology offers moderate speed and power and high complexity and based on either Enhancement (normally off) type n-channel (EnMOS) or, for improved performance, both Enhancement and Depletion type (normally on) n-channel MOSFETS (EDnMOS). Only suitable for digital circuits.
• p-channel MOSFET technology (pMOS) solely not offered any more due to the devices' slow performance compared to nMOS technology because of the lower mobility of the charge carriers (holes).
• Technology based on both p-channel and n-channel enhancement MOSFET known as Complementary Metal-Oxide Semiconductor (CMOS) popular as it offers very low power dissipation, is suitable for both analogue and digital applications but at the expense of lower complexity compared to EDnMOS. CMOS is becoming the standard process for all but the highest speed devices.
• Technology based on both bipolar and CMOS (BiCMOS) can give the best of both technologies but at the expense of increased fabrication complexity and cost. Used in applications requiring aspects of both analogue and digital

1.5.2 Gallium Arsenide

• Inherently material capable of producing much faster transistors than silicon. (higher mobility)
• Based on components which are a variation of field effect transistors known as Metal Semiconductor Field Effect Transistors (MESFET).
• Originally used in very high frequency ICs but now available for very high speed digital circuits of relatively low complexity.
• Expensive compared to silicon ICs, due to more complex fabrication.
• Choice of technology will depend on a number of factors given in the specification, including cost, CAD tools, etc.

1.6 Design Considerations - Architecture

  Several architecture choices available; the main types are:

• Programmable Logic Device (PLD) (semi-custom)
• Gate array (semi-custom) 
• Field Programmable Gate Array (FPGA) (semi-custom) 
• Standard cell (semi-custom). Often called CBIC (Cell-based I.C.)
• Full custom 
• Microcontroller (software controlled)

Note: In semi-custom the designer accepts restrictions in order to simplify the design whereas in full custom the designer is free to optimise each component to improve performance and reduce chip size. This increases cost and design time enormously.

1.6.1 PLD

PLDs are reusable PROM memory devices used in computers where the user programmes an array of transistors/gates to form a given function using an electrical programming device.

• No involvement of IC manufacture.
• Low complexity - up to several thousand gates only
• Cheap and quick but with little flexibility.
• Range of CAD tools available running on PCs.
• Originally digital only but pure analogue arrays now also available.

1.6.2 Gate Arrays

• Gate arrays are arrays of transistors manufactured on-chip but not connected.
• Individual interconnection mask made for each design which is used to 'customise' the arrays.
• Cheap for medium or even low volumes.
• Semiconductor manufacturer has to be involved in the process.
• Typical turn-round times 4-8 weeks.
• High complexity now available up to several million logic gates.
• Available in most technologies.
• High flexibility.
• Originally purely digital but now available with analogue cells giving mixed analogue/digital capability.

1.6.3 FPGA

• Variation of gate array which allows the user to field programme a gate array as in PLD and thus reduce design time.
• FPGAs less dense than gate arrays and therefore higher unit cost but available up to 1 million gates or so.
• Compatible FPGA/gate array device ranges available to enable initial designs to be made using FPGAs and transfer easily to gate arrays later if required.

1.6.4 Standard Cell (CBIC)

• Designer uses a library of standard pre-designed cells stored in a computer and builds up his chip design in that way.
• Highly flexible in allowing cells to be placed, modified and connected giving chip areas typically 10-15% smaller in area compared to gate arrays and hence lower unit costs.
• Since each design fully customised requires the production of a unique full mask set and therefore longer turn-round time (typically 10 weeks) and higher initial (non-recurring) charges and therefore only usually economic at high volumes.

1.6.5 Full Custom

• The chip is specially designed from the beginning giving a design that is fully customised to a given specification.
• Designer effectively works at transistor level but may use pre-defined cells (IP) if suitable.
• Design may take many man-years and therefore very expensive.
• Finished chip is likely to match the specification precisely but at high cost.
• Only economic at very high volumes ( in excess of 100K units/year).

1.6.6 Microcontrollers

• Essentially a microprocessor integrated onto a single chip along with a range of useful functions and controlled by software

1.8 Other Design Considerations

General design approach either 'top-down' - essentially starting from the system requirements or 'bottom-up' - starting from the IC components available to the designer.

Chip area and floorplanning and packaging aspects need to be considered, because chip area usually determines cost and yield while packaging is of concern to the customer and designer alike.

Power supply including operating voltage and current requirements are required in order to design power track widths, electromigration, etc.

CAD tools availability, effectiveness and ease of use important as they will form a key part of the design process, including manufacture.

Test aspects are vital, including the incorporation of Design for Test (DfT) circuitry to enable efficient and effective production testing to take place in a few seconds.

Test costs are becoming a significant part of total chip costs in many cases.  See Graph2:

Graph 2 - Relative cost versus cost breakdown.

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Finally, last but not least, cost considerations have to be taken into account as each of the previous technological, architectural and other considerations have different cost implications.

  For this example this results in a typical cashflow forecast - see Graph 3:

Graph 3 - Balance versus months

Hence the break-even time (27 months in this case) can be estimated.

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