See section A1.1 (of text book) - Semiconductors
See section A1.2 (of text book) - Material Preparation
See section A1.4.1 (of text book) - Diffusion
See section A1.4.2 (of text book)
See section A1.6.1 - Wet etching for 1b). (In particular Figure A1.8). For a) replace metal by silicon dioxide and use subtractive etching only. Additive-lift-off process does not work for silicon dioxide only for metallisation.
See section A1.9.1 (of text book) - Bipolar process - in
particular Figure A1.10 a) the n+ buried layer reduces the
collector series resistance rc and in turn reduces
Vce(sat)
b) the emitter doping has to be highest, next the base, and the collector the lowest in order to maximise gain. But the collector is placed first (epitax layer) followed by the base, followed lastly by the emitter which has to be shallower than the base.
c) gain could be increased by c1) narrowing the gap between the base and the emitter (base width)
c2) increasing the doping of the emitter (not-feasible as the emitter is usually doped as high as possible)
c3) decreasing the base doping so as to increase the ratio of emitter doping to base doping (may cause other parameters to shift out of specification)
c4) use arsenic for the emitter dopant (gives squarer diffusion profile) or better still use ion implantation (gives square profiles).
See section A1.9.3 - CMOS process - in particular Figure A1.12 a) field oxide is 'thick' and therefore ensures that the threshold voltage of any parasitic n (or p) MOSFET formed between n regions (or p-regions) is higher than the normal operating voltage of the devices (say +5v) and thus ensures no conduction between them (isolation between respective transistors)
b) overlap capacitances are minimised by making the gate oxide and poly layer first and then forming the drains and sources around the poly/oxide gate in order to ensure minimum overlap and thus minimise the overlap capacitances (self-aligned gate)