Microelectronic Design

Unit 3 - Integrated Circuit Packaging

Question 1

Renti's Rule is $ckt=\left(\frac{N}{K}\right)^n$

For high performance applications

K = 2.5, n = 1.79

Find N when

ckt = 10,000, 1,000,000

i)

N = 171.6 × 2.5 = 429 pins

Comment: Too large for wirebond. OK for TAB or C4

ii)

N = 2,248.8× 2.5 = 5,622 pins

Comment: Too large for wirebond and TAB and therefore could only use C4,

Question 2

i) Line resistance - causes volatage drops and increases in signal transition times. Also decrease immunity to signal noise, i.e. cross coupling noise and switching (dI) noise.

ii) Reflections - can cause erroneous circuit function. Further problems occur at the junction between the signal line and the stub.

Minimise - package and design to minimise signal line capacitance, line resistance, self-inductance, interline capacitances and inductances. Reduce line lengths. Use low dielectric constant materials.

Question 3

See Table 1-5 in the text book. Use in high performance applications such as processors.