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Microsystems Technologies

Unit 3: Microsystems Processing Techniques - 1

Unit Contents

• 3.1 Introduction
• 3.2 Pattern Replication
• 3.3 Deposition
• 3.4 Etching
• 3.5 Sacrificial Layer Processing
• 3.6 Silicon Planar Technology
• 3.7 Other Materials

3.1 Introduction

There are a number of ways in which we could classify and group the various processes used in MST.  As we have already ascertained, there is much to be gained by using processes compatible with, or based upon, well understood semiconductor processes. These use silicon (almost exclusively) as a base material.  However, MST frequently requires the use of other materials, so we will need additional processes.  It may be useful therefore to discuss MST in terms of silicon processing and specialised processing.  (This has the added advantage that the assigned textbook classifies it in this way).

In this unit, we shall look at the common silicon processes and talk about their suitability for microsystem manufacture.

First of all, let us consider the key processes for microfabrication (note: the terms micromachining and microfabrication are frequently used interchangeably).  These were mentioned at the end of the previous unit and you should try to recall what they are.

We will now discuss them in more detail.

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3.2 Pattern Replication

Automated methods of reproducing patterns are the fundamental process required for almost every mass production technique. (For example, think of the stamping of car body parts in sheet steel).  Traditional methods include printing, moulding, casting and embossing.  Difficulties arise when we try to apply such methods directly to the dimensions required for microsystems.  These lie in:

• the adaptation of the process itself and
• the fabrication of the master or tool

Figure 1: Mask

The fabrication of ICs solves this through the use of a well-established process called photolithography. This consists of the transfer of a pattern on a mask plate to a layer of photosensitive material, usually by means of ultraviolet illumination. This allows very precise reproduction (to sub-micron resolutions).  The use of a series of masks, each aligned to the surface of the material, allows quite complex structures to be fabricated. Typically, the mask will consist of a repeated pattern (in order to fabricate many identical devices at once) on a glass or quartz plate and the working material will be a thin wafer of silicon.

There are two important restrictions:

• The surface of the structure must be planar and...
• The exposing light will be diffracted by the resist.  This limits the thickness (depth) that can be exposed without loss of resolution.

These are a result of the requirement for the sensitive layer to be in contact with the mask or in the image plane of the optical system.  The result is that fabrication based on photolithography is essentially two-dimensional.  As we have discussed, MST often requires three-dimensional features.

A lot of MST research is aimed at overcoming these restrictions of the photolithographic manufacturing whilst retaining its considerable advantages of reproducibility and advanced state of development.  Hence, a lot of MST fabrication is based on Silicon Planar technology.  It starts with a silicon wafer and treats it to a series of patterning, deposition and etching steps to achieve the desired result.

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3.3 Deposition

Another key technique is that of deposition.  As the term suggests, this is essentially a process, which deposits material onto the surface of the wafer.  The main techniques are:

1. Epitaxy.  This is a process whereby a very thin (1-10 micron) layer of doped silicon is effectively grown on the wafer in such a way that the crystal structure is continuous between the substrate and the deposited layer.

2. Vacuum deposition.  By means of thermal evaporation or ion bombardment (known as sputtering), atoms are liberated from a source material in a vacuum chamber and condense on the cool surface of the wafer (or other object).  This technique is often used to deposit thin (< 1 micron) layers of pure metals but can be used for non-metals and mixed materials.  The technique allows precise control of thickness.  However, the atoms travel from the source to the sample in a straight line.  This means that, if the surface is not planar, shadowing will result and the coating will not be of uniform thickness (shown in figure 2 below).

Figure 2: Vacuum Deposition

Other disadvantages are:

a) the deposition rates are low, limiting the applicability for thicker layers
b) A large proportion of the source material is wasted.

3. CVD (Chemical Vapour Deposition):  A gas is passed across a heated sample in a reaction chamber.  The surface of the material reacts with the gas to produce the desired layer.  This technique is commonly used to create layers of Silicon Dioxide (SiO₂), Silicon Nitride (Si₃N₄) and polysilicon with thickness of 1 micron and above.  The result is a conformal coating (where the added layer covers the entire surface - see figure 3 below).  However, the process requires elaborate equipment and is difficult to set up.  There are also safety & environmental concerns owing to the materials used.  (But note that the use of CVD is becoming more widespread for IC processing.  It may, therefore, be subject to rapid development).

Figure 3: Chemical Vapour Deposition

4. Spin coating.  In this process, a vacuum holds the wafer to a spinning chuck.  A liquid is applied which spins out to form a coating.  This dries or polymerises to form a layer of about 100 microns or greater.  There is no precise control and the process tends to planarise a non-planar surface (see figure 4 below).  The technique is commonly used for spinning of photoresist onto silicon wafers where such considerations are less important.

Figure 4: Spin Coating

5. Electroplating.  This can be achieved for conductive surfaces by passing an electric current through an electrolytic bath. Layers greater than 1 micron thickness can be achieved.  The apparatus required is relatively simple, but control is difficult and imprecise.  The quality of the surface is usually poor.  Electroplating can be combined with the photolithograhpic process.  If a patterned photoresist is applied, deposition will not occur where the resist blocks the current.  If a thick layer (or deep feature) is required, the resist layer must be equally thick. (see figure 5 below)

Figure 5: Electroplating

6. Lift-off technique.  This is a combination of Photolithography and Vacuum Deposition.  Basically, the deposition takes place onto a surface patterned with photoresist.  The coating is deposited over the entire surface but, when the resist is dissolved, the coating above will detach.  For this to occur, the edges of the coating must be well defined.  Hence the technique cannot be used with either CVD or spin coating. This can readily be seen from figure 6 below.

Figure 6: Lift-off technique

Before Lift Off  After Lift Off

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3.4 Etching

Etching is basically a means of removing material.  Common, mechanical methods such as milling and grinding are difficult to apply to microsystems (this was discussed briefly in unit 1).  In microelectronics and microengineering chemical methods are much more common.  The main reasons for this are:

• They can be highly selective with regard to the material they etch.
• This means they can be controlled using the photolithographic method with a patterned etch resist layer.
• The use of different etchants and other methods of control (such as doping or etch stops - discussed later) provides a variety of techniques for different effects.

There are two main etching techniques - wet & dry.

Wet etching is the simplest process where the sample is placed in a liquid that dissolves some materials but not others (typically, the mask material or a doped region).  Broadly speaking, etchants can be Isotropic or Anisotropic.  Isotropic etchants attack the material equally in all directions and Anisotropic etchants attack the material at different rates in different directions.  It is particularly useful for cutting deep V-groves and trenches.  We shall look at these in more detail later.

Dry etching uses a gaseous etchant.  The gas is ionised and the ions are propelled to the sample in an RF field.  This is known as Reactive Ion Etching (RIE).  It has a high directionality and allows deep, steep-sided features to be made.

Figure 7: Effects of etching techniques

Typical effects of the two wet and the dry etching techniques are shown in figure 7 above.

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3.5 Sacrificial Layer Processing

This is an extension of the normal silicon IC process to obtain micromechanical structures.  It is often referred to as surface micromachining.  It consists of a series of steps: depositions and patterned etches.  Two or more materials are used and one is finally selectively etched away to leave a free-standing structure.  SiO₂ is normally used as the sacrificial layer and polysilicon or silicon nitride for the structures.  An isotropic, wet etch or RIE can be used for etching.

Note that this technique is closely compatible with conventional IC technology, giving the potential for integration of the electronics in the same device.

These then are the main techniques for micromachining.

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3.6 Silicon Planar Technology

In order to appreciate the processes required for MST, it is important to have a good grasp of the Silicon Planar Process.

In order to remind or familiarise yourself with this, look at the module on Microelectronic Design, unit 2.  In particular, note the process model of diagram 2 and compare it with the way we have categorised the process steps in this unit.

Now read section 3.2 of the textbook by Gardner: Microsensors Principles and Applications.  Note the process steps as set out on page 37.  A couple of important additions are bonding and encapsulation.   Passivation is discussed in section 3.2.6. of the book.  It is important to note here that it is possible to leave a gap in the passivation layer.  With an IC it is necessary to leave such gaps (known as windows) over the metal bond pads to allow bonding to take place.  One important technique we have not explicitly discussed  above is doping.  A good account of this is given in section 3.2.1 and you should go over this carefully.  Figure 3.2 is interesting mainly because it comes from a source dated 1976.  Although it doesn't imply any relative importance of the processes listed, CMOS is undoubtedly the most prominent process today and this is where most research and investment goes.  NMOS & PMOS are by no means extinct, but they are very rare.  One process not mentioned is SOI (Silicon on Insulator).  You may come across  this as SOS (Silicon on Sapphire).

We have from time to time mentioned that much of the research into microsystems is focused on solving the problems of compatibilitiy with common IC production.  The paper by Sniegowski et al gives a short overview of how one team sees the problem of adapting silicon processes and integrating MEMS. The sections of note are those entitled "Integrating MEMS and CMOS" and "Adapting to microsystem manufacture". Figure 3 is interesting. Note the following in particular:

• The discussion of the problems involved.  These are not confined to process techniques but to areas like equipment reliability.
• The reference to packaging as a barrier
• The discussion on reliability

The paper hints at some of the things we shall look at in more depth in the following unit - surface & bulk micromachining.

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3.7 Other Materials

The processes above are generally applied to silicon. Of course, silicon is just one of the materials available to us to construct a microsystem. A number of other materials, both passive and active are used in MST.

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Updated 17.03.05 RA & RJ

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