Microelectronic Technologies and Applications
SPICE EXERCISE
CMOS LOGIC CIRCUIT DELAYS
Preliminary Information
This exercise is likely to be the first time you will have been asked to run Cadence remotely. First you need to install MetaFrame on your PC; click here for instructions.
Read about operating a PC as a Unix terminal, linked from here.
Both the above links are also present in the "Students" site under "IT Configuration". You may find it helpful to bookmark the reference on operating a PC as a Unix terminal as it is likely to be useful in many other modules.
The SPICE exercise below details the simulation and delay analysis of a simple CMOS inverter under no-load and loaded operating conditions. You should expect to spend about two hours on the exercise.
Introduction
The circuit simulators within the CADENCE integrated circuit design system can be used to simulate digital and analogue circuits at the transistor level.
This exercise details the simulation and delay analysis of a simple CMOS inverter under no-load and loaded operating conditions using a variant of the Spice simulator, Spectre.
Conventions Used In This Walkthrough
1) All commands typed at operating system prompts should
be terminated with the RETURN key.
Unix commands must be entered in lower
case unless otherwise stated.
2) Operations involving the mouse will use the left hand mouse button unless otherwise stated.
3) Options selected from sub menus will be indicated as:-
Main Menu option - Sub menu Option - Sub Menu Option
e.g.
File - New - Library
A number of menu options also have keyboard equivalents (bindkeys)
for faster selection.
e.g File
- Open can also be activated by simultaneously using the ^o
keys (^ is the Ctrl key)
These are indicated on the appropriate
menus where available.
Creating a Design Environment
Students using the AMI design system are provided with a Transport menu
that facilitates easy access to appropriate design directories and associated
applications software.
Invoke the Transport menu by typing the following command in the UNIX terminal window :-
transport
The Transport menu appears as shown below.
The menu enables a module design area to be initially created and then entered by specifying the module being studied. Modules are classified by type.
Click on the Technology button
to display a list of modules within that classification.
Select the module A4233
If you are using the CAD system for the first time for this module there
will be no design areas existing..
Click on the Create Module Area
button to create a number of design areas. Only the Walkthroughs
area will be used for this exercise.
Click on the Walkthroughs button
and ensure that the ComputeServer button is set to Beaker
The Transport menu should now be as shown below.
Now click on the Enter Module Area
button to open up a dedicated UNIX module terminal window.
All subsequent commands will be typed in this window.
Starting Cadence
Enter the following command to invoke Cadence
amiselect fb
After a short delay the Cadence Command Interpreter Window (CIW) as shown below will appear at the bottom of the screen. The window provides a tool bar for the top level menu commands and a display window for status information.
The design kit for the Austrian Micro Systems (AMS) fabrication
process will be loaded.
A Select Process Option form is displayed. This is a layout option
and will not be required for this exercise.
Click on the form to fully display and select the Cancel
button.
The Cadence File Manager will also be displayed. The File Manager enables design libraries and cells to be created and manipulated.
Viewing the Single Inverter Schematic
The inverter exercises have already been pre-prepared for you.
Cell cmosinv1 defines a single inverter, cell cmosinv4 defines
a quadruple inverter circuit.
We shall use the File Manager to select and display each circuit.
Locate and select by clicking on the following in the File Manager :-
Exercises_AMS035_2005 in the
Library column,
cmosinv1 in the Cell
column and
schematic in the View column (if required)
The File Manager should now be as shown below.
Select File - Open from the
File Manager toolbar to open the selected schematic (cmosinv1)
Since this file is write protected, the system will display a message to open
for read only.
Select Yes to display the Schematic
Window as shown below.
.
At this point you may wish to minimise all other windows except the CIW to avoid the desktop becoming too cluttered (click on the dot icon at the top right of each window). Any mimimised window can be restored by double clicking on its icon. You may also wish to maximise the Schematic Window (click on the square icon at the top right of the window).
The schematic defines a simple CMOS inverter consisting of one PMOS and one NMOS transistor. The channel widths and lengths of both transistors are set to the minimum process dimensions (3 microns). The device will be operating under no load conditions from a 5 volt power supply. A pulsed voltage source of 4ns duration at the input will test the device in both of its operating conditions. The rise and fall times of this pulse have been set comparable to those of the device (0.5ns).
Setting up the Simulation
The simulation will be performed using the Spectre simulator.
This is located in the Analog Design Environment section of Cadence.
Select Tools - Analog Environment from the schematic window
The Cadence Analog Design Environment form will appear as shown below with spectre selected as the simulator
Before the simulation can take place it will be necessary to set up the parameters for a transient analysis. A transient analysis plots a graph of a selected circuit voltage or current against time. The parameters define a length of time for which the simulation should run. Since the applied input pulse has a 1ns duration the simulation must proceed at least to the end of this pulse. A stop time of 3.5ns will be adequate.
Select Analyse - Choose [or the AC/TRAN/DC icon second down on the right] from the Analog Design Environment form to display the Choosing Analyses form.
Select the tran button from
this form and enter a value of 12n
into the Stop Time box.
The form should now be as shown below :-
OK the form and check that the parameters have now been entered into the Analyses section of the Analog Design Environment form as shown below
Running the Simulation
Select Simulation - Run [or the green traffic light icon] to run the simulation.
The first time a simulation is run the system will display a Spectre
Welcome message.
Having read the message click the "Do not
show this text again" button
This avoids repeated occurrences of the message.
Select OK on the message toolbar
to run the simulation
During the simulation, status information and any possible error messages
are displayed in the CIW.
You can maximise the window to see all of this information.
Check the messages to verify that the simulation has terminated successfully
At the end of the simulation, a window will open displaying the simulation
log file.
The file contains useful information about the simulation run and error conditions
should the simulation be unsuccessful. You may see warnings relating to the
model parameters. These can be ignored.
Select File -Close Window to
close the window.
Displaying the Simulation Results
Select Results - Direct Plot - Transient Signal from the Analog Design Environment form
An empty Waveform Window will be displayed with the schematic window eventually overlayed on top.
The Schematic Window now enables signals to be selected for display.
The input from the pulse generator and the circuit output will be displayed.
Click anywhere on the input wire or pin labeled in
A successful selection will highlight the wire in a new colour.
(Avoid clicking on the connecting dots, this will not register)
Click anywhere on the output wire or pin labeled out
Again observe that the wire highlights in a new colour.
The schematic should now be as shown below.
Press the Esc key to terminate
the selection process
The selected waveforms are now displayed in the Waveform Window as
shown below.
The window can be enlarged to full size if desired by clicking on the square
icon in the top right hand corner of the window.
The waveforms can be viewed more easily by splitting the display.
Select Axes - To Strip from
the Waveform Window to produce the display shown below
Measuring the Single Inverter Timings
The time taken for the output of a device to switch to its opposite logic state upon the application of an input signal is referred to as the Propagation Delay. For a single logic element, this propagation delay is defined by how fast the output can switch between states. The time taken to achieve this is known as the Switching Time. The switching time for a low to high transition of the output is referred to as the Rise Time whilst that for a high to low transition defines the Fall Time. When several devices are connected in series in a logic circuit these switching times become additive. Logic designers (and logic simulators) use the device switching times to calculate overall propagation delays for the circuit. Outputs rise and fall exponentially due to the charging and discharging of device capacitances. You can observe this on the simulated output waveform, particularly in relation to the rising edge. Since the time taken to reach a new steady voltage level can be lengthy, rise and fall times are conventionally measured between 10% and 90% of their voltage swing
To obtain accurate measurements for the output rise and fall times it will
be necessary to isolate and enlarge the output waveform.
Select Curves - Edit from the
Waveform Window to display the Curves form.
The form enables waveforms to be selectively displayed.
We shall remove the input waveform from the display.
Select the input waveform VT("/in")
in the Curve Name column so that it highlights.
Click the off button.
The form should now be as shown below with the waveform's Display
column entry set to off.
OK the form and observe that only the output waveform is now displayed.
You may also wish to remove the plot points on the waveform (known as ticks)
to obtain a smoother curve
Select Curves - Options from
the Waveform Window to display the Plot Style form
Enter 0 into the Number
of Ticks box as shown below,
OK the form. The display should now be as shown below:
The zoom facility is used to enlarge the waveform.
The first area of interest is the waveform's falling edge
Select Zoom -Zoom In from the
Waveform Window
Position the cursor at the top left of the zoom area (i.e. near the top
of the falling edge of the waveform).
Press the left hand mouse button.
Drag the cursor to the bottom right of the zoom area (i.e. near the bottom
of the falling edge of the waveform).
Press the left hand mouse button again.
The zoom function will now be activated and the display should be as shown
below.
The display can be returned to normal size at any time by selecting Zoom - Fit.
Crosshair Markers are useful for taking timing measurements from the waveform.
Select Markers - Crosshair Marker A
from the Waveform Window.
Position marker A at the top of the falling edge at a voltage of 4.5 volts
(90% marker).
The current location of the marker is displayed as an x/y co-ordinate at the
bottom of the window.
Press the left hand mouse button to lock the marker
Select Markers - Crosshair Marker B
from the Waveform Window.
Position marker B at the bottom of the falling edge at a voltage of 0.5 volts
(10% marker).
Press the left hand mouse button to lock the marker
Should you wish to unlock the markers for re-positioning, simply re-select the Markers option.
The display should now be as shown below:
The delta reading at the bottom of the window indicates the time difference
between markers.
This is the fall time and will be of the order of 0.31ns .
Display the entire simulation again by selecting Zoom
- Fit.
Repeat the above procedure for the rising edge of the waveform.
This is the rise time and will be of the order of 0.80 ns.
The rise time is longer than the fall time because the PMOS and NMOS transistors have been defined on the schematic as having identical channel dimensions. Since the mobility of holes in the PMOS device is typically two to three times less than that of electrons in the NMOS device, the PMOS device will take proportionally longer to switch.
From the above timings we can therefore determine that the device propagation
delays under no-load conditions are :-
For a low to high transition = 0.80ns
For a high to low transition = 0.31ns
Select Window - Close from the
Waveform Window to close down the waveform window
Leave all other windows open
Simulating the Quadruple Inverter Circuit
The quadruple inverter circuit utilises four of the previous single inverter
cells connected in series.
Delays inherent in the circuit will now be noticeably longer. In particular
there will be :-
a) Increased switching delays for each transistor caused by the additional input capacitance of its driven load.
b) Increased overall propagation delay with 4 devices in series.
Both these effects will be observable by simulation.
Select Design - Open from the Schematic Window to display the Open File form.
Click on the cell name cmosinv4 in
the Cell Names list and check that it appears in the Cell Name
box.
Click on OK and select Yes
to open the file for read only.
The circuit is now displayed as shown below.
Click in the Cadence Analog Design Environment form.
Select Setup - Design to display
the Choosing Design form as shown below
Select the cmosinv4 cell and
OK the form.
Select No in response to the
query "Do you want to save the current state?"
This would normally save your simulation parameters but is not necessary
for this exercise.
The design specified in Analog Design Environment form will now be reset to cmosinv4.
Follow the same procedure as established for the single inverter to simulate
the circuit.
Use the same transient analysis parameters.
Select and display the waveform at the circuit input, the first, second and third inverter output wires and the final circuit output.
The display should be as shown below
Measuring the Quadruple Inverter Timings
Temporarily remove all waveforms from the display (Curves
- Edit option) except the output of the first inverter (net34).
Measure the new rise and fall times.
Verify that the fall time under loaded conditions has increased to the order
of 0.57 ns
Verify that the rise time under loaded conditions has increased to the order
of 1.79 ns
From the above timings we can therefore determine that the device propagation
delays under loaded conditions are:-
For a low to high transition = 1.79ns
For a high to low transition = 0.57ns
Remove this waveform from the display and re-instate both the input and output waveforms as shown below.
Observe that the total propagation delay through the four inverters is considerably
longer than that for the single inverter. Logic simulators calculate this
delay by adding together the loaded propagation delays for each of the logic
elements.
From the timings previously obtained, the delays for this circuit would be
:-
For a low to high transition = 0.57ns + 1.79ns + 0.57ns + 0.8ns = 3.73
ns
For a high to low transition = 1.79ns + 0.57ns + 1.79ns + 0.31ns
= 4.46 ns
(Note: the final inverter has no load)
The above figures will be approximate. In actual fact the circuit dynamics are quite complex. Devices will begin to switch when their input signal reaches the threshold voltage. Using the full rise and fall times in calculations implies a switch near to full value. Rise and fall times on device outputs are also dependent on the rise and fall times of their inputs. The analysis assumed a constant input rise / fall time of 0.5ns which is only true for the first inverter in the circuit. Both these effects can be observed on the previous waveform display where all device inputs and outputs are selected.
Leaving CADENCE
It is good practice to exit applications software in an orderly fashion and leave a clean UNIX desktop
Select Window - Close in the Waveform Window to close the window.
Select Window - Close in the Schematic Window to close the window.
Select Session - Quit on the
Analog Design Environment form to quit the simulator.
The message " Do you want to save the current state ?" will be displayed.
This provides the option to save your simulator settings if required.
Select No to complete the quit
operation without saving.
Select File - Exit on the CIW
to exit Cadence.
The message "OK to exit icfb?" will be displayed.
Select Yes to complete the exit
operation.
Click on the - icon at the
top left of the UNIX Module terminal window.
Select Close from the pull down
menu.
Select File - Quit in the Transport Window to close the window.
You can leave the UNIX terminal window open for your next session.
Now click on the Exit
button on the Unix desktop to logout from the Common Desktop Environment.
Confirm the logout when requested.
Updated 24.01.06 JO