Useful Tools

contact us contact tutor/group email to a friend accessibility options report a fault
Microelectronic Technologies & Applications

Microelectronic Technologies and Applications

Unit 1: CMOS Digital Logic

This chapter reviews aspects of ASICs and the process involved in designing and fabricating them using the common CMOS process. This leads to the design and implementation of common logic cells found in most digital designs including combinational, sequential, and I/O cells.


Unit Contents


1.1 Introduction

An Application Specific Integrated Circuit (ASIC) is one type of silicon integrated circuit (IC) or chip. Other types are memories (DRAM and SRAM), microprocessors and standard devices. In essence ASICs are devices made for a specific application such as a mobile phone.

Commercial ICs are enclosed in a package, which can either be made from ceramic or plastic. The silicon chip itself is typically 1cm square and contain several million transistors. A 2-input NAND gate requires 4 transistors in CMOS so often the number of gate equivalents is quoted (typically a million gates in 0.13um technology).

For more information on the development of ICs read the first section of chapter 1 of the text-book. (Application-specific Integrated Circuits
by Michael John Smith, ISBN: 0201500221, Publisher: Addison Wesley web: www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/ASICs.htm)

There are many types of ASICs so we will now have a brief look at each.

1.1.1 Types of ASICs

All ASICs are fabricated on silicon wafers (typically 8- 12 inch diameter) by building up layers with different semiconductor characteristics in order to produce transistors. The process used to define certain areas is masking , which is a process akin to very high definition photographic printing. Typically lines of minimum widths 0.13um can be produced hence the technology is referred to as 0.13um. The wafers are then cut into individual die and mounted in an IC package. In total the production of an ASIC takes typically 8-10 weeks.

A full custom chip is all made specifically and uniquely for one application , is very expensive and only economic at very high volumes (millions/year).

To make ASICs economic at lower volumes the semi-custom concept was introduced where many applications share the same basic configuration of logic cells – it is only the final interconnect stage that is different to give the different chips. There are several types of semi- custom ASICs – in succeeding sections we will look briefly at each type.

1.1.2 Full custom ASICs

In full custom the designer essentially works at the transistor level designing sub- systems and systems to meet his specification precisely. The chip may have up to 100M transistors so very complex designs can be made. He may use predefined cells if they are available and suitable but, in gerneral, all/ parts of the design have to be designed in this way. Therefore full custom is slow (even with the use of modern CAD tools) and typical design times for a large full custom chip can be several hundred man-years or more. It follows therefore that full custom designs are very expensive and the initial cost can only be recouped if the chip volumes are very high.

As digital systems are usually not very critical for correct operation full custom design of logic systems in not normally required these days.

However in analogue and mixed analogue/digital systems where the matching and electrical characteristics are still very critical full custom is still quite commonly used.

For more info read section 1.1.1 in the text book.

1.1.3 Standard cell based ASIC (or cell-based IC CBIC)

This approach uses pre-defined standard logic cells (gates, flip-flops etc) and larger blocks such as processors, which are pre-defined and characterised. The designer simply has to build up his design(which may be very large typically over 1M gates) in this way using powerful CAD tools, which makes the whole process quicker and cheaper and makes designs implemented in this way economic at lower volumes (typically 100k units/year) than full custom albeit at a loss of some flexibility for the designer.

Figure 1.1: Physical layout of a CBIC design.

Physical layout of a CBIC design

(from Application-Specific Integrated Circuits (fig 1.2) by MJS Smith - permission requested)

Reference Texts

For more information read section 1.1.2 in the text book

1.1.4 Gate array ASIC (channelless array or sea of gates array)

In this case the transistors are arranged as a regular array on the ASIC and the designer has only to design the final interconnect pattern using logic cells in a cell library and powerful CAD tools. See Figure 1.2. One type – known as Field Programmable Gate Arrays (FPGAs) - can be programmed by the user using a fuze type technology as used in PLDs (see next section). For further information on FPGAs read section 1.1.8 in the textbook.

Figure 1.2: Gate array ASIC

Gate array ASIC

(from Application-Specific Integrated Circuits (fig 1.6) by MJS Smith - permission requested)

There are many variants of the basic gate array including a channelled array (where the rows of cells are separated by a channel essentially to make the interconnect easier), a structured gate array (which combines some aspects of CBIC and the gate array).

In essence gate arrays remove more of the design process from the ASIC designer, making the process simpler and quicker at a loss of further flexibility. Hence complex designs are possible in gate arrays, which are economic at lower volumes still (typically 20k units/ year or lower).

For more information on gate arrays read sections 1.13 – 1.1.6 in the textbook.

1.1.5 Programmable logic devices (PLDs)

PLDs have been around for quite some time. They are based on ROM or PROM technology, are limited to a small number of gate equivalents, typically 1000, and are very easy to programme using PLD software such as PALASM or CUPL. Essentially all PLDs consist of an array of OR gates and an array of AND gates with some macrocells which are usually latches of flip-flops. Depending on the type one or other or both arrays are user programmable.

PLDs are very simple to use and reduce time/costs to very low levels making a PLD solution economic at 100 gates or lower.

For more information please read section 1.1.7 in the textbook.

[back to top]


1.2 ASIC Design Flow

The sequence of steps in designing an ASIC (design flow) is shown in Figure 1.3. The steps will now be listed and a brief description given of each.

Figure 1.3: Sequence of steps in designing an ASIC (design flow)

Sequence of steps in designing an ASIC (design flow)

(from Application-Specific Integrated Circuits (fig 1.10) by MJS Smith - permission requested)

  1. Design entry
  2. Logic synthesis
  3. System partitioning
  4. Simulation
  5. Floorplanning
  6. Placement
  7. Routing
  8. Circuit extraction
  9. Post layout simulation

Reference Texts

For further information please read section 1.2 in the textbook.

[back to top]


1.3 Case Study

Case Study

Please read the case study on the Sun Microsytems SPARCstation in section 1.3 in the textbook.

[back to top]


1.4 ASIC Cost Comparisons

The economics of using ASICs in a product is an important consideration. Different ASIC solutions have different fixed costs and variable costs. To make realistic cost comparisons, costs must be up-to-date as they change often. In the example we use 'typical' costs to illustrate the differences.

Figure 1.11: A break-even analysis for an FPGA, a masked gate array (MGA) and a custom cell-based ASIC (CBIC). The break-even volume between two technologies is the point at which the total cost of parts are equal. These numbers are very approximate.

A break-even analysis for an FPGA.

(from Application-Specific Integrated Circuits (fig 1.11) by MJS Smith - permission requested)

Figure 1.15: Example price per gate figures.

Example price per gate figures

(from Application-Specific Integrated Circuits (fig 1.15) by MJS Smith - permission requested)

Exercise

Carry out the EXCEL Spreadsheet Exercise

[back to top]


1.5 Cell Libraries

[back to top]


1.6 Websites of Interest

Internal & External Links

Flextronics

EDN

EDAC

Semiconductor Industries Association

Sematech

Fabless Semiconductor Association

[back to top]


1.7 CMOS Inverter

Reference Texts

See chapter 2 in the textbook

Figure 2.1: CMOS transistors as switches

CMOS transistors as switches

(a) An n-channel transistor. (b) a p-channel transistor. (c) A CMOS inverter and its symbol (an equilateral triangle and a circle).

(from Application-Specific Integrated Circuits (fig 2.1)
by MJS Smith - permission requested)

Figure 2.4: MOS n-channel transistor characteristics for a generic 0.5mm process (G5).

MOS n-channel transistor characteristics for a generic 0.5mm process (G5).

A short channel transistor, with W = 6 mm and L = 0.6 mm (drawn) and a long channel transistor (W = 60mm, L = 6mm)

(from Application-Specific Integrated Circuits (fig 2.4)
by MJS Smith - permission requested)

[back to top]


1.8  CMOS Process

[back to top]


1.9  CMOS Design Rules

[back to top]


1.10 Logic Cells

1.10.1 Combinational

Reference Texts

See section 2.4 in the textbook.

1.10.2 Sequential

Reference Texts

See section 2.5 in the textbook

1.10.3 Datapath Logic Cells

Reference Texts

See section 2.6 in the textbook

              Sum  = A  CIN
    and Cout   = A.B + A.CIN + B.CIN

           Sum  =  PARITY (A,B,CIN)
    and Cout  =  MAJORITY (A,B,CIN).

1.10.4 Datapath Cells

1.10.4.1 Adder

Reference Texts

See section 2.6.1 and 2.6.2 in the textbook

Figure 1.21: Symbols for a datapath adder.

Symbols for a datapath adder.

(a) a data bus is shown by a heavy line and a bus symbol. If the bus is N-bits then MSB = n-1. (b) An alternative symbol for an adder. (c) Control signals are shown as lightweight lines.

Figure 1.22: The Ripple Carry Adder (RCA).

(a) A conventional RCA. The delay may be reduced slightly by adding pairs of bubbles as shown to use two-input NAND gates.

(b) An alternative RCA circuit topology using different cells for odd and even stages and an extra connection between cells.

The carry chain is a fast string of NAND gates (shown in bold).

Figrue 1.26: Datapath adders.

This data is from a series of submicron datapath libraries.
(a) Delay normalized to a two-input NAND logic cell delay (approximately equal to 250ps in a 0.5mm process). For example, a 64-bit ripple-carry adder (RCA) has a delay of approximately 30ns in a 0.5mm process. The spread in delay is due to variation in delays between different inputs and outputs. An n-bit RCA has a delay proportional to n. The delay of an n-bit carry-select adder is approximately proportional to log2n. The carry-save adder delay is constant (but requires a carry-propagate adder to complete an addition).
(b) In a datapath library the area of all adders is proportional to the bit size.

1.10.4.2 Multipliers

Reference Texts

See section 2.6.4 in the textbook

1.10.4.3 Other datapath operations

Reference Texts

See section 2.6.6 in the textbook

1.10.5 I/O Cells

Reference Texts

See section 2.7 in the textbook.

Figure 1.33: Popular tri-state bi-directional output buffer

Popular tri-state bi-directional output buffer

1.10.6 Compiled Cells

Reference Texts

See section 2.8 in the textbook.

Self Assessment Questions

Please attempt problems 1.2 - 1.6 in section 1.7 of the textbook.

Show solution

Self Assessment Questions

Please attempt questions 2.3, 2.4, 2.5, 2.6, 2.7 (not f), 2.12, 2.14(i), 2.18, 2.19, 2.21, 2.23, 2.24, 2.25, 2.27, 2.28, 2.29, 2.20, 2.31 (first part) and 2.34.

Show solution

[back to top]

Updated 20.06.06 RA

Site Search

Powered by Google
Site Map