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Microelectronic Technologies and Applications

Unit 1: CMOS Digital Logic

Self Assessment Answers

Answer 1.2

No. of gates = 20k + 50k + 9k + 5k + 3k + 9k + 4k + 1k + 1k
No. of gates = 102k gates

No. of transistors = 102k × 4 = 408k transistors

Engineer's time = 5 x 6 months    =   30 engineer months
                                                     or  30 x 20 = 6000 engineer days

 

Productivity = \frac{102k}{6000} &=& 17 \mbox{ gates / engineer day}\\ \mbox{ or } &=& \frac{408k}{6000} = 68\mbox{ transistors / engineer day}= 17 gates / engineer day
                                                      or = <image> = 68 transistors / engineer day

Figures in 1.12 are 5000 gates/day (FPGA), 200 (CBIC + MGA)  ie. much higher than the SUN figures.
Probably because  the SUN engineers were using slow, outdated software and most of the ASICs would have been full custom.

Productivity figures are not particularly accurate - they are average figures and probably + 20% at best.

Answer 1.3

As an illustration use the first package in Table 1.4  ie.  44 lead PLCC.  - maximum die size  =  320 × 320 mil

With no I/O pads, no. of gates  = \frac{320 \times 320}{1} = 102,400 \mbox{ gates} = 102, 400 gates

Number of pads ?  Assume pads are 20mil.square and spacing of 5 mil.

\frac{320}{25} = 13 = 13 on a side or 13 × 4 = 52 altogether

If spacing 10 mil. between pads No. of pad = \frac{320}{30} = 11 = 11 ie. 44 altogether

Equals the number of pins in the worst case of 10mil. spacing.

Minimum number of gates?

Minimum die size = 94 × 94 mil.

No. of gates = \frac{94 \times 94}{1} = 8836 gates assuming no pads.

If we assume worse case pads ie. 20 mil square + 10 mil separation
\frac{94}{30} = 3 = 3 on a side or 12 in total.

But the actual gate area is now 94 - 30 - 30 = 34 mil

\No. of gates = \frac{34 \times 34}{1} = 1156 gates

Similar calculations can be done for other packages.

Answer 1.4(a)

Yield = 70 + 0.2 (W-80)% = 70 + 0.2 (100-80)%
Yield = 74%

Answer 1.4(b)  

Good parts = 100 wafers x 100 \mbox{ wafers} \times \frac{74}{100} \times 200 x 200 = 14,800 parts/week

Just enough to meet Mr Big's and Mr Smart's requirements.

Answer 1.4(c)

To supply Ms Teeny also.  Needs 1200 parts/week ie.  extra 8 wafer starts.
New yield is 70 + 0.2 (108-80) = 75.6%  But this applies to all products,

No. of good parts = 108 x 108 \times \frac{75.6}{100} \times 200 x 200 = 16,329

but only 16,000 needed, so could get away with only 106 wafer starts/week to give required number of parts.
(Yield now drops to 75.2%) so the number of parts is :

106 x 106 \times \frac{75.2}{100} \times 200 = 15,942 \mbox{(not quite enough).} x 200 = 15, 942 (not quite enough). 

107 wafer starts OK - need an extra 7

Answer 1.4(d)

Sumo's increase in costs to supply Ms Teeny?

Wafer costs = $ \$\left[500 + \frac{250,000}{100}\right]100 100 = $300,000

with increased wafer starts:

Wafer costs  = $ \$\left[500 + \frac{250,000}{107}\right]107 107 = $303,500 an increase of $3,500

Answer 1.4(e)

Revenue increase = $3,500 × 1.35 = $4,725

Answer 1.4(f)

Charge Mr Big $0.5 more per part
Revenue = 10,000 parts × $0.5 = $5,000/week

Answer 1.4(g)

Ms Teeny extra business.  How much does it reduce wafer cost?

BEFORE    
   Wafer cost was $3,000
   Now cost is $2,836
   \Reduces it by $164

Answer 1.4(h)

How much can Sumo afford to lose on Ms Teeny to cover costs and make 35% profit?

Sumo's costs are $303,500

Revenue - Currently $300,000 × 1.35 = $405,000

But costs go up to $303,500 which for 35% profit requires $409,725 Therefore, can take a loss of $409,725 - $405,000  =  $4,725  or  \frac{4725}{1200} = $4/part  

Answer 1.5

Density of silicon = 2.33kg/m3
6 inch wafer typically 0.5mm thick

Weight = Pr2 × thickness × density
Weight = 3.14 × (7.5×10-2)2 × 0.5 × 10-3 × 2.33
Weight = 2.06 × 10-5kg

12 inch wafer typically 1 mm thick

Weight = 3.14 × (15x10-2)2 × 10-3 × 2.33
Weight = 1.64 × 10-4kg

Boat with twenty 12 inch wafers weighs 20 × 1.64 × 10-4kg = 3.28 × 10-3kg

For mechanical strength and stability, particularly at high temperatures, the boat needs to be at least 10 - 20 times the weight of the wafers ie.  0.1 - 1.0kg.  Therefore, furnace has to be capable of withstanding kgs of weight.

Answer 1.5(a)

12 inch wafer - no. of die 1 inch on a side.

No. of die = \pi\frac{(R-\sqrt{A})^2}{A}  (See module 02 Chapter 8 Exercise 2)

No. of die = 3.14 3.14\frac{(15-\sqrt{6.25})^2}{6.25}
 

20 wafer boats are worth $100 × 78.5 × 20 = $157,000 if all good + the price of the boat.

If 10 boats have to be scrapped, money lost is $157,000 × 10  = $1.57million

Answer 1.5(b)

Value of factory production

A = 500 mil = 1/2 inch × 1/2 inch = 1/4 inch2
No. of die/wafer = \pi\frac{(R-\sqrt{A})^2}{A} = 3.14 3.14\frac{(6-\frac{1}{2})^2}{\frac{1}{4}}
No. of die/wafer = 380 die

No. of good die/week = 380 × 0.9 × 5000 = 1.71M
Each die worth $20 gives value of $34.2M / week OR $1778.4M/year ($1.778B) assuming 52 week operation.

Fraction of GDP of UK
GDP UK is £11,000 × 58M =£638B OR $1020B

Fraction is \frac{1.778B}{1020B} \times 100 x 100 = 0.17%

Yield drops 40%, what is the revenue lost per day?

No. of good die/day (90% yield) = \frac{1.71M}{7} = 0.24M

No. of good die/day (40% yield) =  \frac{380 \times 0.4 \times 5000}{7} =  0.109M

Revenue lost  =  $2.62M/day

Cash reserve of $100M

Company goes out of business in \frac{100M}{2.62} = 38 days  

Answer 1.5(c)

TSMC

6 inch wafer.  Die are 500 mil  (0.5inch) or 0.25inch2
No. of die wafer  = 3.14 x 3.14 \times \frac{(3 - 0.5)^2}{0.25} = 78

Total in 1996 = 2M × 78 = 156M die.

Camar fab plant

Yield = \mbox{Yield} = \frac{\mbox{No. of good die}}{\mbox{Total die}} = \frac {1500 \times 100}{1700} = 88\%= <img> = 88%

Die size (A) No. of die =  \mbox{Die size (A) No. of die} &=& \pi\frac{(R-\sqrt{A})^2}{A} \\ 1700 &=& 3.14\frac{(4-\sqrt{A})^2}{A}
                          1700 = 3.14 <img>

0 = 16 - 8 0 = 16 - 8\sqrt{A} + A - 541.4A + A - 541.4A  - Equation 1

Solve for A  - iteratively

Guide
No. of die = square wafer equivalent Area × 2 = \frac{64}{2A} =  1700

A = A = \frac{64}{2 \times 1700} = 0.019\mbox{inch}^2 = 0.019inch2

Substitute in Equation 1 to test.  Answer about 40% too low say A  = 0.0266inch2
Test is nearly correct \chip area is 0.0266inch2 or 0.16inch on a side.

A  =  0.0266inch2  = 0.0266 x 0.0266 \times \frac{(1)^2}{39}\mbox{m}^2 m2 =  1.75 × 10-5m2

Each RAM cell is 7µm2 and there are 1m
\RAM cells area is 7 × 1 × 106 >= × 106µm2  = 7 × 106 × 10-6 × 10-6m2
\RAM cells area is 7 \times 1 × 106 ?= × 10-6m2

 \ Fraction of die taken by RAM is \frac{> \times 10^{-6}}{1.75 \times 10^{-5}} = 0.4 \mbox{ or } 40\% = 0.4 or 40%

Cost per bit for SRAM if wafer cost is $2000
Wafer gives 1500 good die or 1500 × 1M good RAM bits

\Cost/bit = = \frac{\$2000}{1500M} = 1.33 \times 10^{-6}\$\mbox{bit} = 1.33 x 10-6$bit

16Mb DRAM on same line uses 16mm2 die.  Cost per bit for DRAM assuming same yield?

No. of die/wafer = \pi\frac{(R-\sqrt{A})^2}{A} = 0.162

No. of die/wafer = 0.16

3.14 3.14\frac{(10-\sqrt{0.16})^2}{0.16} = 3.14\frac{(10-0.4)^2}{0.16} = 1808\mbox{ die} = 3.14 <img> = 1808 die

Same yield ie. 88%

No. of good die  =  1808 × 0.88  = 1591

Cost per bit = \frac{\$2000}{1591 \times 16m} = 7.85 × 10-8 $/bit

Answer 1.6(a)

Real time = 3 seconds

20MHz clock, period = \frac{1}{20M} =  5 × 10-8 or 50ns

So simulated time is \frac{3}{50 \times 10^{-9}} = 60M slower than real time.

Answer 1.6(b)

To simulate 400 lines.  Assume one line/cycle  ie.  4000 × 50ns  =  200µs simulated time
OR 200µs × 60M = 33\frac{1}{3} hours real time.

Answer 1.6(c)

5 ms of code would take 5 × 10-3 × 60m seconds  =  300,000 seconds or 83 hours or 3.47days

Answer 1.6(d)

Booting on UNIX work station - how long?
Probably a few seconds (<10 seconds).

How many clock cycles?
= \frac{10s}{\frac{1}{200} \times 10^6} =  2000M clock cycles assuming 200 MHz clock.

Answer 1.6(e)

Typically 10% say of time executing boot code  ie. 200M lines of code or 200M clock cycles assuming 1 clock cycle/line of code.

Answer 1.6(f)

Simulate booting takes 200M clock cycles@ 50ns clock equals 10 seconds.
Takes 10 seconds × 60M seconds real time  =  600M seconds  OR 6944 days!!! Due to slow clock!

Answer 1.6(g)

No

Answer 1.6(h)

Probably not due to the complexity and the incomplete simulation of the ASICs.