Microelectronic Technologies and Applications
Unit 1: CMOS Digital Logic - Self Assessment Answers 2
Answer 2.3 (a) Q = C (VGC - VtN)
Answer 2.3 (b) Charge is negative but an extra minus sign comes from tf
Answer 2.3 (c) For p-channel, charge Q gives the extra minus sign.
Answer 2.4 Evaluate kn using method described in p44
Answer 2.5(a) gamma =
Top = 
= 
Bottom = 
= 34.51 x 10-4
\gamma = 5.79 x 10-4
= 0.167
34.51 x 10-4
Answer 2.5 (b) VEN = VEON + gamma
If VSB = 0 , VtN = 0.5 =
VEON
If VSB = 1 , VtN = 0.5 + 0.5 
= VtON
If VSB = 2 , VtN = 0.5 + 0.5 
= VtON etc.
Answer 2.5 (c) Linear approximation to VtN above
Answer 2.5 (d) VtP = VtOP - gamma
Answer 2.5 (e) Since bulk connected to source for both transistors no back bias effects
Answer 2.6 Size = X x Y. Use scale to get transistor sizes.
Answer 2.7 (a) Overall process yield = (0.9)100 = 2.6 x 10-5
Answer 2.7 (b) Overall yield 90% ; individual stage yield = X
then (X)100 = 0.9
X = 
Answer 2.7 (c) 500 microtasks
then X =
Answer 2.7 (d) Microtasks yield is 0.9998 ie. 2 mistakes in 10,000 or 1 in 5,000
5 tasks / day \ 5,000 tasks in 1,000 days ie. around 3 years
Answer 2.7 (e) Not really. Model assumes mistakes all equally likely to occur whereas some more likely and some less
ie. average yield assumed.
Answer 2.12
Answer 2.12 (a)
n well , 200l x 1.15K = 70KW etc.
3l
Answer 2.12 (b) Resistance of slice
Thickness - assume 0.7mm typical
Then R = 10 x 20
= 142W
20 x 0.07
Face to face R = 0.07 x 10
= 2.2 x 10-5W
3.14 x 10,000
Answer 2.14 (i) n channel , VtN = 0.5v, bn = 40 x 10-6
VGS = 3.3v
Answer 2.14 (a) VDS = 3.3v
VGS - VtN = 3.3 - 0.5 = 2.8
\ VDS > VGS - VtN ie. saturation
\ IDS = bn (VGS - VtN)2
= 40 x 10-6 (3.3 - 0.5)2
= 1568mA.
2
2
Answer 2.14 (b) VDS = 0v
\ VDS < VGS - VtN ie. ohmic
then
= 40 x 10-6 [ (3.3 - 0.5)2 - 0] 0 = 0
Answer 2.14 (c) VGS = 0, VDS = 3.3V
then VGS - VtN = 0 - 0.5 = -0.5 ie. VDS > VGS - VtN ie. saturation.
hence IDS = 40 x 10-6 (0 - (-0.5))2 = 5mA
2
Answer 2.15 Would not work
Answer 2.18(a) F = 1
Answer 2.18(b) F = 1 - 3VtN
Answer 2.18(c) S of M1 = 5V
D of M1 = 4.4V
S of M2 = 4.4V
D of M2 = 3.8V
S of M3 = 3.8V
D of M3 = 3.2V
Answer 2.18(d) If VDD = 3V, then voltage at D of M3 will be 0.2V - circuit will not work
Answer 2.18(e) Stops working when voltage at F ceases to be recognised as logic 1 (+2.4V)
Answer 2.21
| Ratio would be | 8500 400 | i.e. 21:1 |
ratio than n device to compensate.
Answer 2.23 See pages 68 + 70
Answer 2.24 C(4) = G(4) + P(3) G(3) + P(3) P(2) G(2) + P(1) P(3) P(2) G(1) + P(4) P(3) P(3) P(1) G(0)
C(8) = G(8) + P(7) G(7) + P(7) P(6) G(6) etc. (9 terms) See equation 2.57
Answer 2.25 See Figure 2.13
Answer 2.27 See Figure 2.13
Answer 2.28 Latch is transparent (input changes appear at the o/p in the unlatched state), flip-flop is not.
Answer 2.29 Set-up and hold times are transparent
Answer 2.30 tsu is minimum time to keep data stable prior to clock edge.
th is minimum time to keep data stable after clock edge.
Do not agree with statement from Clemenz Portmann
Answer 2.31 Diff =
Note: Equation 2.71 is wrong, the last term should be BIN not CIN
Answer 2.34 (a) Input voltage clamped to a voltage less than breakdown voltage - can withstand ESD because of the low amount of current involved. If the pin was shortened to a +10v then the current and charge will be much higher and would blow the device.
(b) Again it is the current that kills - current from the mains is much higher than from static.