Online Postgraduate Courses for the Electronics Industry

Provided By The University of Bolton

• Home
• About Us
• Questions & Answers
• Courses
• Students
• Links

Useful Tools

Microelectronic Technologies and Applications

Unit 2: Time delay and power dissipation considerations

Unit Contents

• 2.1 Chapter Overview
• 2.2 Gate Delay
  • 2.2.1 Transistor parasitic capacitances
• 2.3 'Logical Effort' Delay Model
  • 2.3.1  Logical area
  • 2.3.2  Logical paths
  • 2.3.3  Optimum delay
  • 2.3.4  Optimum number of stages
• 2.4  Library Cell Design
• SPICE Exercise (involves remote access)
• 2.5 Power Dissipation
• Self Assessment

Author: Professor Ted Pritchard

Textbook: Application Specific Integrated Circuits, MJS Smith

For tutor support in the main chapter contact: Neil Cole

For tutor support in the SPICE exercise contact: Neil Cole

Notional Workload: 10 hours

2.1 Unit Overview

This chapter covers two important aspects of CMOS ICs, namely gate delay and gate power dissipation. Physical parameters within the gates that determine the values for the two parameters in practice are discussed as are methods of estimating values from calculation and CAD tools.

As ASICs and all integrated circuits are comprised basically of millions of logic gates then overall chip delay (which is the inverse of operating frequency) and chip power dissipation are ultimately determined by the individual gate delay and gate power dissipation.

In recent years with technology developments, in particular scaling down to 0.13µm and soon to 0.9µm (90 nm) it is now possible to buy Intel Pentium 4 processors operating at 2.66 GHz compared to 100 MHz or less only 5 years ago. Power dissipation has similarly reduced although current processors still require heatsinks and forced cooling

[back to top]

2.2 Gate Delay

• In most ASIC design styles it is necessary to use cells from a standard library.
• Some knowledge of the characteristics of the library cells is required when using them in designs.
• Layout and propagation may not be adequately modelled
• In practice a CMOS inverter has a propagation delay between input changing and the resulting output change which is a function of gate capacitances and resistances.
• Often modelled in terms of the non-linear resistance of the transistors and total capacitance (see Figure 2.1).

Figure 2.1: A model for CMOS logic delay

• Although no current is taken by a CMOS inverter under static conditions (logic 1 or 0), current is drawn during switching due to both transistors being on (see Figure 3.2 in textbook). Modern DSM designs i.e. 65-45nm have gate oxides of the order of 25-30 Angstroms. In modern designs leakage through the gate oxide, predominately fowler nordling tunneling means that gate leakage comprises of 1/3 to 1/2 of the total current consumption of a circuit.
• Switching delay often given driving standard loads (gates) where n = 1, 2, 4, 8 etc.
• Simulation shows that switching delays are approximately linear function of load capacitances - see Figure 3.3 in text book (and hence the number of loads).
• Typically delay time (falling) tpdf = Rpd (COUT + Cp) - equation 3.2
• Delay time (rising) also follows equation 3.2
• Due to complexity it is only possible to evaluate time delays accurately from CAD simulation (eg. SPICE)
• Hand calculations only give very approximate values (typically ±25% error)

2.2.1 Transistor parasitic capacitances

• As previously described, cell delay results from transistor resistances, transistor (intrinsic) parasitic capacitances and load (extrinsic) capacitances.
• Input capacitance of driven cell is the load capacitance of the driving cell.
• CAD tool SPICE typically lists 8 capacitances for a CMOS transistor (shown diagrammatically in Figure 3.4 in text book).
• Junction capacitances CBD and CBS are p-n diode capacitances.
• Overlap capacitances CGSOV, CGBOV and CGDOV are oxide capacitances, and account for lateral diffusion of drain and source under the gate. Cell libraries quote values (typical)
• Gate-source, gate-drain and gate bulk capacitances, CGS, CGD and CGB are combinations of junction and oxide capacitances.
• Detailed formulae for calculating each capacitance is given in Table 3.1 together with a typical calculation at one operating condition.
• All transistor parasitic capacitances are functions of operating conditions, particularly voltages.
• For instance, Figure 3.5 in textbook shows the variation of all the parasitic capacitances with VIN from 0 to +3V.

[back to top]

2.3 'Logical Effort' Delay Model

Originally suggested by Sutherland and Shroull (1991) based on the time constant analysis of Mead, Seitz and others.

• 'Logical effort' is a concept which gives us an insight into why logic gates have the delays they have and allows us to examine relative delays.
• Modifies equation 3.2 by an additional term tq to give tpd = R (COUT + Cp) + tq which is equation 3.10.
• tq is non-linear and includes delay due to parasitic capacitances and other effects.
• For scaled cells (scaling factor s) since capacitances increase and resistances decrease then equation 3.12 results giving

tpd = (COUT + sCp) + stq.

• Equation 3.12 is then rewritten using the capacitance of the scaled cell - equation 3.14 and normalising the delay d, using the pull resistance RINV and input capacitance CINV of a minimum size inverter giving equation 3.15 where

d =    = f + p + q         3.15

• and

T = RINV CINV

• So delay (d) is the sum of the effort delay (f), parasitic delay (p) and non-ideal delay (q).
• Effort delay (f) is further broken up into the product of logical effort (g) and electrical effort (h).
• Logical effort is defined in figure 2.8 and is a function of the type of logic cell.

Figure 2.8: Logical Effort

• Table 3.2 gives logical efforts for inverter, NAND and NOR cells.
• Section 3.3.1 in the textbook shows how to use this technique to calculate the delay in a 3 i/p NOR gate driving a net with capacitance 0.3pF giving an answer of 0.846ns.

2.3.1 Logical area

• Enables a calculation of the area of transistors in a logic cell to be made - logical area (see section 3.3.2).

2.3.2 Logical paths

• Calculation of delay in the earlier sections did not depend on logical effort g because it is not driving the NOR cell with another logic cell which is ideal.
• In a logical path situation it is possible to calculate the delays of logic cells driven by a minimum size inverter.
• Path delay, d, is the sum of the logical effort, parasitic delay and non-ideal delay at each stage.
• Extend this concept to work out delays in multistage cells. (See section 3.3.4)

2.3.3 Optimum delay

• Path logical effort g is the product of logical efforts on a path.
• Path electrical effort h is the product of electrical efforts on the path.
• Path effort F is the product of g and h.
• Optimum effort delay can then be found.
• Logical effort is useful in the design of logic cells and in the design of logic using logic cells.

2.3.4 Optimum number of stages

• For a chain of N inverters each with equal stage effort f, then neglecting parasitic and non ideal delay  it can be shown that minimum delay occurs when electrical effort h is equal to 2.7.
• Shown diagrammatically and in a tabular form in Figure 2.12

Figure 2.12: Stage Effort (f)

[back to top]

2.4 Library cell design

Designers use cell libraries - they are themselves developed usually by specialised companies or chip manufacturers.

• Use hand-crafted or more commonly, symbolic layout, to draw the cell layout.
• Particular design rules built-in.
• Cells for gate array, standard cell and datapath are quite different - see section 3.6, 3.7, 3.8 and elsewhere in this course.

[back to top]

2.5 Power Dissipation

• Power dissipation in CMOS logic arises from three sources:
  • i) dynamic power dissipation due to switching current charging/discharging parasitic capacitance
  • ii) dynamic power dissipation due to short-circuit current when both transistors are momentarily on(crowbar current) .
  • iii) static power dissipation due to leakage current and sub-threshold current.
• Switching current power dissipation (P₁) given by f C VDD² and is traditionally the major source of power dissipation in CMOS.
• Reduce by reducing supply voltage VDD and parasitic capacitance C.
• Short circuit current (crowbar current) power dissipation (P₂) can be important for output drivers and large clock buffers
  and is given by

  P₂ =   (VDD - 2VtN)³

• Typically P₂ is 20% of P₁
• Sub-threshold current in CMOS is less than 5pA/mm of gate length but for a large ASIC containing > l00K transistors it gives a total current of 0.1mA.
• Similarly the reverse-biased diodes conduct a very small leakage current - typically 1-5mA for a 100,000 transistor ASIC.
• Both currents constitute the very low static power dissipation of CMOS. As the scaling continues leakage current effectively increases making power dissipation due to leakage potentially the largest contributor to total power. Typically 10mW total for a 100,000 transistor CMOS ASIC (0.5 um technology).
• Minimising power dissipation becoming very important because large complex ASICs containing potentially millions of gates require very low power dissipation/gate in order that the total package dissipation level is not exceeded. Also important for battery-driven equipment eg. mobile phones.

Low Power design has become a major concern of all ASIC and IC designers in recent years because of cooling, packaging and reliability considerations. Design techniques such as asynchronous design, although essentially more complex than the usual synchronous design is more power efficient because the power hungry clock circuitry is a major part of the total power consumption on chip. Other techniques used are switching parts of the system off when not in use, using lower power technologies and architectures.

Modern CAD tools now include power estimator tools at high/low levels to enable the designer to evaluate the power dissipation aspects of his design very early on in the design process and make changes as required.

For recent information on low power design issues access the web-site of the European Low Power Initiative for Electronic System Design at http://vada.skku.ac.kr/ClassInfo/microsystem/cad-alg/de-synopsis.html (previously: www.esdlpd.dimes.tudelft.nl ). This initiative also published several books on specialist areas of Low Power Design through Kluwer Academic Publishers.

For instance the book, The principles of Asynchronous Circuit Design by Sparso and Furber (ISBN 0-7923-7613-7) is an excellent text for anyone wishing to learn about Asynchronous Design. Those interested should also review the Philip's tools designed to support such design.

A number of Asynchronous design books are available via the Netbooks interface via the University catalogue for those interested in pursuing the topic further. From personal experience it is interesting, challenging and a way to terrify your manager by asking if you can do a section as an asynchronous design ( Neil ).

[back to top]

Partially Updated Neil Cole 30.08.11

Site Search

Powered by Google
Site Map