Microelectronic Technologies and Applications
Unit 2: Time Delay and Power Dissipation Considerations
Self Assessment Answers
Answer 3.1(a)
for small VDS (linear region)
Then 
if
VGS = VDD1 VDS
= 0
Answer 3.1(b)
Answer 3.2
Answer 3.3
Answer 3.4
Logical effort, g, of AoI 122 cell.
Use the method shown in figures 2.13 and figure 3.8
Gives that 
Answer 3.18
Replace one inverter in both master and slave by two input NAND cells (figure 2.18a). For active low set replace I2 and I9; for active low reset replace I3 and I6. For MUX implementation use single 2 input MUX instead of a pair of NAND cells.
Answer 15.15(a)
Power P = f CVDD2
5 = 100 x 106 x C x 25
or
C = 
But this is only 20% of
nodes \Total
C = 
Answer 15.15(b)
Interconnect capacitance = 0.5 x 10-8F which gives
interconnect length
= 
Answer 15.15(c)
Power in I/os = f C VDD2 = 50 x 106 x 20 x 10-12 x 100 x 25
= 2.5 W
Answer 15.15(d)
3 x 106 transistors = 
gate equivalents
Answer 15.15(e)
20% of nodes toggle every clock cycle.
ie. 20% of gates switch every clock cycle
or 
gates every clock cycle.