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Microelectronic Technologies and Applications

Unit 3: Simple Programmable Logic Devices (SPLDS)

Unit Overview

This chapter introduces a group of custom silicon components known collectively as Programmable Logic Devices. Typical generic architectures are considered with particular reference to the construction, principle of operation and application of those devices categorised as Simple Programmable Logic Devices.

Unit Contents

• 3.1 Introduction to Programmable Logic Devices
• 3.2 Basic Principles
• 3.3 PROM Architecture (Fixed AND Array, Programmable OR Array)
• Self Assessment Questions 1
• 3.4 PLA Architecture (Programmable AND Array, Programmable OR Array)
• 3.5 PAL Architecture (Programmable AND Array, Fixed OR Array)
• 3.6 Simple Programmable Logic Devices (SPLDs)
• Self Assessment Questions 2

Author: Jeff Ormerod of Bolton Institute

For tutor support contact: Neil Cole

Notional Workload: 10 hours

Textbook: Application-specific Integrated Circuits
M.J. Smith

3.1 Introduction to Programmable Logic Devices

Programmable Logic Devices (PLDs) offer a low cost, low risk route into customised silicon for digital circuit implementations. They are particularly suitable for small volume production (typically < 1000 units /year) or where a higher volume but fast time to market is required.

Devices are supplied from the manufacturer with an array of prefabricated logic components and interconnect. The designer utilises a CAD system to define the required configuration of components and interconnect for a given design.

Unlike mask programmable devices that require fabrication at a silicon foundry, PLDs are electrically programmable by the user. Typically this is implemented by downloading the configuration data from the serial line of the CAD system either directly into the device or via a device programmer.

Device architectures vary considerably from the simple AND/OR gate structure of small PLDs to the complex logic cell arrays of Field Programmable Gate Arrays (FPGAs). Device types are further distinguished by being either one time programmable (OTP) or re-programmable.

Most manufacturers will also offer hardwired versions of their devices in which the interconnect circuitry is removed in favour of single tracks. This reduces silicon area and therefore device cost and would be an appropriate consideration for higher volume production (typically > 10,000 units/year).

Programmable Logic Devices are available in a wide range of architectures and sizes. They are generally classified into three groups of increasing capacity, features and cost as follows :-

• Simple Programmable Logic Devices  (SPLDs)
• Complex Programmable Logic Devices  (CPLDs)
• Field Programmable Gate Arrays  (FPGAs)

The Department of Trade and Industry's Microelectronics in Business seminar presentation provides an overview of the technical and business issues involved in utilising programmable logic technology.

It is recommended you view the presentation before continuing this chapter.

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3.2 Basic Principles

The simplest form of PLD comprises an AND array driving an OR array as shown in Figure 1.

Figure 1: PLD Device Array Structure

Each AND gate in the example has 6 inputs whilst each OR gate has 8. Inputs to gates are often represented as single lines for clarity. A matrix of input signals (true and inverse via input buffers) is therefore formed at the input to the AND array with a second matrix being formed at the input to the OR array.

This mode of construction is ideally suited to implementing logic expressions of the form :-
        _ _ _    _ _       _   _                        _ 
F = ABC + ABC + ABC + --------- ABC + ABC (REDO AS EQUATION)

often referred to as Sum of Products expressions.

Connections to gates in each array matrix can be fixed or programmable. A fixed connection is hardwired whilst a programmable connection is implemented by a fusible link. Devices are supplied by the manufacturer with all fusible links intact. The device is customised to implement the required logic functions by blowing those fuses where connections are not to be defined.

Three possible device architectures can be constructed depending on whether a matrix is fixed or programmable.

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3.3 PROM Architecture (Fixed AND Array, Programmable OR Array)

The simplest form of PLD comprises an AND array driving an OR array as shown in Figure 1.

Figure 2 shows a construction that defines a Programmable Read Only Memory (PROM) with 8 memory locations and four separate output functions. 

Since the AND array is fixed, each of the 8 combinations for the three input variables I₂, I₁ and I₀ effectively defines a memory address.

For an array with n inputs, 2ⁿ AND gates will be required.

Only one AND gate will be active for any given input combination so each of the outputs O₃, O₂, O₁ and O₀ will register a logic 1 or logic 0 depending on whether the corresponding fuse in the OR array is left intact or blown.

Logic expressions are therefore being defined by storing a complete truth table in the PROM for each of the 4 functions required. The limitation of this type of architecture is the inefficiency incurred when large numbers of input variables are required. A sixteen variable function for example would require a 64K location PROM and would occupy far more silicon area than a discrete logic gate implementation.

Self Assessment Questions

Use the checkboxes on the right of each truth table to express a value for F.

means a value of 1.
means a value of 0.

Part 1.

Part 2.

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3.4 PLA Architecture (Programmable AND Array, Programmable OR Array)

Figure 3 defines a Programmable Logic Array (PLA) structure with 3 input variables and 4 output functions. 

Having both arrays programmable allows greater flexibility in generating logic functions, particularly when more than one output function requires the same product term. In this case the AND gate generating the product term is simply connected to the appropriate OR gates. 

However, should a particular logic function require a large number of product terms this can quickly use up the available supply of AND gates leaving few left to implement the other functions 

The major disadvantage of the PLA structure is related to having an extra set of fuses in the OR array which adds extra propagation delay to the signals and reduces the component packing density. For this reason examples of commercially available devices are limited. 

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3.5 PAL Architecture (Programmable AND Array, Fixed OR Array)

Figure 4 defines a Programmable Array Logic (PAL) structure with 6 input variables and 4 output functions.

The basic PAL structure is the exact opposite of that required for a PROM.

The number of AND gates required is considerably reduced from the 2 n needed for the PROM and is related only to the number of product terms to be defined.

The fixed OR array, however, imposes restrictions on the number of product terms than can be logically ORed together and therefore limits the complexity of the required logic expressions.

PAL devices provide the optimum compromise for speed, flexibility and packing density and offer many features such as programmable input/output pins, internal feedback from outputs, flip flops and active LOW/active HIGH outputs that make them ideal components for implementing logic functions.

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3.6 Simple Programmable Logic Devices (SPLDs)

There exists a bewildering array of terminology amongst manufacturers for this group of devices. Often they are simply referred to as PLDs. The PAL devices previously discussed fall into this category. More complex devices are sometimes referred to as Erasable Programmable Logic Devices (EPLDs) although some manufacturers use this as a generic term to cover all programmable devices.

PAL devices form the entry level into the group, typically replacing 5 or 6 TTL chips in a 20 or 22 pin package. They provide a good introduction to the features, architecture and applications of SPLDs.

The PAL was invented at Monolithic Memories Incorporated (MMI) in 1978 to provide an alternative to Small Scale Integration (SSI) chips in applications where customised combinational or sequential logic is required. In its original form it employed bipolar technology and fusible links for programming.

Amongst the first devices to be offered were the PAL18H8 (a combinational device constructed from an AND/OR array structure) and the PAL16R8 (which added flip flops to enable sequential circuits to be implemented).

The modern equivalent is the PAL16V8 manufactured in CMOS technology and combining features from both these devices. The programming fuses are replaced by electrically programmable cells, thereby allowing the device to be repeatedly reconfigurable.

Programming is accomplished by placing the device in a device programmer and downloading the configuration data file from the serial line of a CAD system. The file conforms to an internationally agreed format known as JEDEC.

The programmer configures the device by re-designating the input and output pins to programming functions. This is achieved by applying a higher than normal voltage to a specified input pin to select programming mode.

The address of the cell to be configured is placed on a subset of the input pins and its required state (logic 0 or logic 1) is set as an appropriate voltage on the output pin connected to the AND/OR block it resides in. The cell is configured by applying a programming pulse to a second specified input pin and the cell state read back on its corresponding output pin to verify correct programming has occurred.

A security bit is provided in the device, which when set during programming, inhibits any reading of the device contents.

The simple AND/OR array construction of PAL devices provides consistent and easily predictable propagation delays through the logic elements, an important requirement  in speed critical applications. Architectures that exhibit this property are often referred to as Deterministic.

Modern PLD/PAL's usually termed CPLD, now include registers allowing for the implementation of Finite state machines rather than just boolean equations.

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Partially Updated Neil Cole 30.08.11

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