Microelectronic Technologies and Applications
Unit 3: Simple Programmable Logic Devices (SPLDs)
Self Assessment Questions
Answer 5d
For this particular device the path is as follows:-
The Path for the particular device
An accurate calculation would be obtained by 1/(tF+ tM+ tB+ tA+ tO+ tS)
where tF
= flip flop delay
tM= multiplexor delay
tB= buffer delay
tA= AND gate delay
tO= OR gate delay
tS= flip flop set up time
No information on these individual delays is available. However the data sheets lists:
tPD
- Set up time from input pin to flip flop clock = 10ns
tCO
- Flip flop clock to output pin = 10ns
Since there are 3 logic elements (flip flop, output multiplexor and output buffer) making up tCO we can approximate that each element contributes 10ns/3 = 3.3ns of delay so that the delay through the flip flop and the feedback multiplexor (tF+ tM) will be 2 x 3.33ns, ie. approximately 7ns.
The path from the feedback multiplexor (tB+ tA+ tO+ tS) onwards has the same number and type of logic elements as those making up tPD = 10ns.
Therefore the maximum operating frequency = 1/(10ns + 7ns) = 58.8MHz.