Microelectronic Technologies and Applications
Chapter 3: Simple Programmable Logic Devices (SPLDs)
Self Assessment Questions
Question 2
An SPLD from the AMD range of devices has been specified with the following code: PALLV22V10-15JC Determine:
a) The type of device.
b) The programming technology
c) The operating voltage range
d) Maximum number of inputs
e) Maximum number of outputs
f) Output polarity
g) Device propagation delay
h) Package type
i) Operating temperature range
Question 3
For the device specified in Question 1 determine:
a) Number of inputs on each AND gate
b) Number of programmable connections for the AND array
c) State of the programmable connections for unused AND gate inputs
d) State of the programmable connections for unused OR gates.
e) Number of output modes
f) Number of available inputs if 8 outputs are used
Question 4
A 4 bit comparator as shown below is to be implemented on the device of Question 1.
A 4 bit comparator
Estimate the % utilisation of:
a) Logic resources
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b) Pinout resources
Question 5
The bit cyclic synchronous counter shown below is to be implemented on the device of Question 1.
Bit cyclic synchronous counter
Functional operation
a) Verify that implementation of the counter is possible
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b) Estimate the % utilisation of logic resources
c) Estimate the % utilisation of pinout resources
d) Calculate the maximum operating frequency of the counter