Digital Integrated Circuit Design
Digital Designer's Guide
Unit Contents
- 1 Introduction
- 2 Combinational Primitive Functions
- 3 Combinational Macrofunctions
- 4 Sequential Primitive Functions
- 5 Sequential Macrofunctions
- 6 System Level Design
1 Introduction
At first sight designing digital circuits would seem relatively simple and straightforward. Well defined logic elements such as AND gates, OR gates, FLIP FLOPS etc. provide a set of primitive logic functions from which a complete digital system can be constructed. In any type of integrated circuit the implementation of the design at the silicon level is always constructed from a mass of transistors that define these primitive logic elements. In all but the simplest of circuits however, designing at the primitive logic level is slow, tedious, error prone and in most cases impractical. Generic design techniques involving truth tables, Boolean algebra, Karnaugh maps etc. often prove inadequate in handling even modest levels of complexity. A better approach is to utilise these techniques to construct higher level functional building blocks. These are often referred to as macrofunctions. For example, we can combine a number of AND, OR and INVERTER elements to form a single bit adder macrofunction. In turn these macrofunctions can be arranged and connected in an appropriate fashion to define a complete design at the system level. In an integrated circuit design flow these macrofunctions are often provided in a cell library or as synthesisable VHDL/Verilog code. In either case a good working knowledge of their design and construction is essential. A required function may not be available in a cell library so will have to be designed and circuit schematics synthesised from high level code will need to be evaluated for speed and area efficiency. The first part of this guide reviews digital design at the primitive level and considers a range of appropriate macrofunctions.
Designing at the system level is a much more difficult skill to acquire. There are no equivalents to the generic design techniques so useful at the primitive level. We start with a blank schematic screen or an empty VHDL/Verilog source file and a construction set of macrofunctions. Courses on digital design and text books on the subject invariably opt out at this point assuming that a knowledge of the basic building blocks implies an inherent ability to combine them into a reliable working system. The essential attribute required here is an aptitude to think functionally rather than structurally. Unfortunately electronic designers have been traditionally educated to concentrate more on how a design is constructed rather than how it should function. Thus we are more comfortable at the primitive level where we can see the structural arrangement of the components than at the system level where we are required to partition the design and define the main functional blocks. However things are changing. High level behavioural languages such as VHDL and Verilog are designed to describe the function of digital hardware and are making a major contribution to promoting this way of thinking. For those utilising these techniques the process of system level design will be increasingly more natural and intuitive. The second part of this guide illustrates digital design at the system level and defines an appropriate design methodology for use in an integrated circuit design flow.
2 Combinational Primitive Functions Combinational
Combinational Primitive Functions Combinational designs are constructed from a set of primitive logic elements for which the design system will provide schematic symbols, simulation models and physical layout data in a cell library. The basic primitives are shown below.
Figure 1: Combinational Primitive Functions Combinational Designs
Not all of these elements will necessarily be available. It depends on what is most suitable to implement at the circuit level in the required technology. For example, a particular bipolar process provides only NOR gates from which the designer must derive all other functions as follows.
Figure 2: Combinational Primitive Functions Combinational Designs
In a CMOS process the circuits for NAND, NOR and INVERTER
are the easiest to implement so the AND and OR functions will
be derived. To make the construction of the design easier
these derived functions are also generally included in the
library.
In addition the derived set will usually be extended to provide
a range of additional inputs for the AND, NAND, OR and NOR
elements. Gates with 3 to 8 inputs are common. Often the buffer
and inverter elements will also be provided in increasing
levels of drive capability since these are commonly used to
source heavily loaded signals such as clocks and resets.
A range of more complex derived elements is often also provided. Below are some examples.
Figure 3 Combinational Primitive Functions Combinational
As before these are constructed from the basic primitives but will normally be implemented on the silicon as complex gates in order to optimise switching speed and minimise silicon area.
3 Combinational Macrofunctions
Combinational Macrofunctions Macrofunctions provide the basic building blocks for system level design. They can be provided by the vendor in a cell library or can be constructed by the designer and added to the library. Combinational macrofunctions include comparators, multiplexors, encoders, decoders, adders etc. The design techniques used in the construction of combinational macrofunctions are illustrated below.
Example: Design a 7 segment BCD to decimal decoder macrofunction
1) Derive a specification for the macrofunction
Figure 4 Derive a specification for the macrofunction
Each segment output is required to provide a logic 1 if the digit to be displayed requires that segment to be active. For example, the digit 3 requires segments a,b,c,d and g to be active. Input codes above 9 should leave the display blank.
2) Obtain minimised logic equations for the required outputs
This can be done either by utilising Boolean algebra or by Karnaugh map. The latter is preferable since it is less prone to error and can yield a more minimised logic function. The following Karnaugh map is defined for segment 'a'.
Figure 5: Minimised logic equations for the required outputs
The minimised logic expression is obtained by grouping together as many logic 1s as possible horizontally and/or vertically in adjacent quares. Groupings will be in powers of 2.
Read off the variables in each group that are the same value in each square of the group to form the product terms of the logic equation.
It is left to the reader to complete the exercise for the remaining segments.
3) Implement the logic equations in the required technology
We shall assume a digital design system with a primitive logic cell library
Figure 6: Digital design system with a primitive logic cell library
Logic Implementation for Segment a
The limitations of this method soon become apparent, particularly
when the number of inputs becomes large and a Karnaugh map
of sufficient size becomes impracticable. In this situation
other techniques are worth considering. Unit 2 of this module
outlines the use of map entered variables as a means of extending
the capabilities of the Karnaugh map.
4. Sequential Primitive Functions
The basic primitive element for sequential circuits is the flip-flop, itself derived from an arrangement of AND, OR and INVERTER combinational primitives. The entry of data into these devices can be controlled either by a signal level (Level Triggered) or by a signal edge (Edge Triggered). The distinction between these two modes of operation is important. The use of the wrong type of device in a circuit can generate serious timing hazards causing the design to fail. The following are the most commonly used devices in each category.
Level Triggered Flip Flops
In a level triggered flip-flop data is entered into the device during the time that the inputs are at an active level. Often these types of devices are referred to as Latches to distinguish them from the edge triggered variety.
S-R (Set-Reset) Latch
Figure 7 Level Triggered Flip Flops
The NOR gate construction of the device enables its operation to be analysed. Inputs S=R=0 retain the current contents of the device. The device can be reset (Q = 0) or set ( Q =1) by setting inputs R and S respectively to logic 1. When S=R=1 both outputs are set to 0. A number of observations can be made from the operation of this device which are equally applicable to most other types of flip-flops.
- The output that is assuming the logic 0 state will be the first to change. The other output will follow later in time, delayed by the propagation delay of the logic element in its feedback loop. Consequently both outputs can never change simultaneously and the output first to change will depend on which way the device is switching. These effects become particularly troublesome when combinational logic is added to the output of all types of flip-flops, such as in counter design for example. The switching delays inherent within the flip-flops are guaranteed to generate spikes and glitches on the combinational circuit outputs.
- Although this is a level triggered device, in normal operation a level will be asserted for a finite length of time so it's really a pulse. The width of this pulse is critical to the successful operation of the device and is related to the total propagation delay through the logic elements of the circuit. An input pulse that has a width less than this delay is likely to cause Metastability. This is a condition in which the flip-flop assumes an illegal state halfway between a logic 0 and a logic 1 for a random length of time. The designer must therefore be aware of minimum pulse width requirements and must ensure that the circuit is properly toleranced. Logic simulators enable varying pulse widths to be defined and are ideal for determining these requirements.
- Most of the time during normal operating conditions the inputs will change state at different points in time. The designer must be aware of what may happen if the inputs change simultaneously. This type of device is particularly susceptible to the condition in which both inputs assume the logic 0 state simultaneously. Under these circumstances the device assumes an unpredictable next state, it may enter a metastable state or may even oscillate.
S-R Latches are most useful in control applications where
we need to set a flag in response to some condition and reset
it when the condition changes.
D (Data) Latch
Figure 8 Internal Construction
The device is defined by a clock input (C) and a data input (D). When the clock is inactive (logic 0) the flip-flop retains its current state. When the clock is active (logic 1) the value on the data input is entered into the device and appears on the Q output. The NQ output is always the inverse of Q. The set (S) and reset (R) inputs perform the same functions as in the S-R flip-flop. Often a box will be inserted at the clock input of the device symbol to indicate a level triggered operation. The following observations should be considered when using this device.
- During the time the clock input is active the value on
the data input is immediately transferred to Q. For this
reason this type of device is often referred to as a Transparent
Latch. Under these conditions the device output will
mirror the data input. This can have disastrous results
in situations where the output can feed back to the input
via some combinational logic thereby repetitively changing
the state of the device and inducing what is know as a Race
Hazard. Also activation of the clock input coincident
with spikes and glitches present on the data input will
result in these being transferred to the output.
- A critical condition occurs when the clock input is being
de-activated (the falling edge). Should the data input change
at this point the state of the device will be unpredictable
and may become metastable. For this reason the designer
must not allow the data to change within a period of time
before this edge (Setup Time) or after the edge
(Hold Time).
D Latches are most useful as storage devices in applications where data has to be retained, such as input and output buffers, processor registers etc.
Edge Triggered Flip Flops
In an edge triggered flip-flop data is entered only when the clock input is changing state. This can be from a low to a high (Positive Edge Triggered) or from a high to a low (Negative Edge Triggered).
D (Data) Flip Flop
Please roll over the symbol below to see its internal construction
Figure 9: Edge Triggered Flip Flops
As before the device is defined by a clock input (C) and a data input (D). When the clock is inactive (logic 0) the flip-flop retains its current state. When the clock defines a low to high transition ( positive going edge) the value on the data input is entered into the device and appears on the Q output. The NQ output is always the inverse of Q. The set (S) and reset (R) inputs perform the same functions as in the S-R flip-flop. Often a chevron will be inserted at the clock input of the device symbol to indicate an edge triggered operation. The following observations should be considered when using this device.
- The state of the data input is captured ONLY at the point in time when the positive going clock edge appears. This is accomplished as shown in the internal construction of the device by having a Master D latch feeding into a Slave D latch. During the time that the clock is a logic 0 the master is open and transparent whilst the slave is closed. When the clock goes to a logic 1 the master closes and the slave opens. At this point the data currently in the master will be transferred to the slave. Although the slave is now operating in transparent mode its entered data from the master remains constant since the master is not now receiving new data. The net effect is that the device output (ie the output of the slave) changes state only at the positive transition of the clock.
- As with the level triggered D Latch care must be taken to observe the device setup and hold times. In this case these times apply before and after the positive going clock edge respectively. A change of input between these times can cause the device to become metastable, assume an unpredictable state or oscillate.
- The set and reset inputs on these type of devices are usually asynchronous. This enables the device to be placed in a defined state at any point in time. This is particularly useful, for example, when initialising all flip-flops in a design to logic 0 on power up Should the set or reset input be activated coincident with the clock edge the set/reset inputs will always take priority. Devices are also available with synchronous set/reset inputs. Here a clock edge coincident with an active set/reset input will be required. These devices should be used with caution since if the existence of a clock edge at the required point in time cannot be guaranteed there will be no way of achieving a defined state.
- Inverting the polarity of the clock applied to the master/slave arrangement within the device will define a negative edge triggered flip-flop. In this case data will be captured when the clock transition goes from high to low.
D flip-flops have universal application in all areas of digital
system design.
J - K Flip Flop
Please roll over the symbol below to see its internal construction
Figure 10 J - K Flip Flop
The J - K flip-flop was originally designed to solve the problem created when the set and reset inputs of an S - R device are asserted simultaneously. Developed versions of this device usually have separate set and reset inputs performing their normal functions with additional J - K inputs to define the data entry. The special case is when J = K = 1. In this condition the device toggles to its opposite state. The following observations apply.
- As the internal construction shows the toggle condition is achieved by effectively opening a path from the inverse output of the device to the input ready for the next clock edge.
- The usual setup and hold times for edge triggered devices apply
- Typically the set and reset inputs will be asynchronous
- Negative edge triggered devices are also available
An often quoted application for J - K flip-flops is in state machine design where logic equations have to be derived for the next state combinational logic feeding the device inputs. Having more "don't care " conditions available simplifies the logic compared with D flip-flops. However, two sets of logic equations are required for each flip flip compared with only one for D flip-flops so the design methodology is more complicated.
T (Toggle) Flip Flop
Please roll over the symbol below to see its internal construction
Figure 11 T (Toggle) Flip Flop
In a T Flip-flop the output changes to its opposite state on every triggering edge of the clock.
These devices are most useful in counter design where a particular flip-flop is required to toggle.
It can be seen from the internal organisation of the J - K and T flip-flops that both these devices can be constructed from D flip-flops. It is quite common, therefore, to see these devices omitted from integrated circuit cell libraries. In these circumstances the designer will be provided with a comprehensive selection of D flip-flops from which all other required functions can be derived.
Both level and edge triggered flip-flops can also be provided
with an additional ENABLE input. This can be used to inhibit
the clock when the device is not required to be activated
on every clock edge. Always use this facility in preference
to gating clocks with combinational logic in areas of the
design where this functionality is required.
5. Sequential Macrofunctions
Sequential macrofunctions include registers, counters, shifters etc. The design techniques used in the construction of sequential macrofunctions are illustrated below.
Example: Design a 3 bit Gray Code Counter
1) Derive a specification for the macrofunction
Figure 12: Sequential Macrofunctions
The essential requirement of a Gray Code counter is that only one output changes from one state to the next. This is particularly useful when decoding the counter outputs with combinational logic to avoid spikes and glitches. An asynchronous reset is used to initialise the counter to the zero state and state changes occur on the positive going edge of the clock.
2) Construct a Present State/Next State table
For the logic implementation of the counter we shall use
D flip-flops so the present state will be the current outputs
of the flip-flops (Qa,Qb,Qc) and the required next state will
be the current inputs of the flip-flops (Da,Db,Dc). Upon the
assertion of the next positive going edge of the clock the
next state will become the new present state.
3) Derive the steering logic equations
Counter design conforms to a standard construction as shown below.
Figure 13 Sequential Macrofunctions
The steering logic is defined by a set of combinational circuits that process the current state of the counter and generate the required next state values. The state latches are the counter flip-flops that define the required state sequence.
The design of the steering logic requires logic equations for Da, Db and Dc. These are derived using a similar technique to that employed for combinational macrofunction design. A separate Karnaugh map is constructed for each steering logic output taking the state sequence as the truth table.
4) Implement the logic equations in the required technology
Again we shall assume a digital design system with a primitive logic cell library
Figure 14: Sequential Macrofunctions
Logic Implementation for Grey Code Counter
As in combinational macrofunction design the limitations of using Karnaugh maps become apparent when counter sizes exceed 4 bits. As suggested before an alternative is to use the map entered variable techniques described in Unit 2. In sequential design large counter lengths are often constructed from smaller blocks connected in series so it's not common to find macrofunctions that are greater than 8 bits.
6 System Level Design
System Level Design Primitive level functions and their derived macrofunctions provide the essential building blocks for system level design. At this level, however, every design will be different so the standard design techniques so far discussed will be of limited use. We require a methodology in which the design is specified top down and implemented bottom up. To specify the design we construct a system block diagram which details the main functional blocks. We can then break down each of these blocks into lower level functional blocks until we reach the macrofunction/primitive level. To implement the design we construct circuitry for each of these lower level blocks and combine them together to define the complete system.
Integrated circuit design systems have always enforced this methodology in order to handle the complexity of modern designs. Schematic symbols can be generated for functional blocks at all levels and simulation of these is encouraged to minimise design errors. More recently designs described in functional languages such as VHDL and Verilog have reinforced these principles by requiring the main system blocks to be described functionally then combined structurally.
A system level design methodology is illustrated below.
Example: Design an 8 bit Pulse Code Modulation (PCM) Transmission System
1) Derive a specification for the system
Figure 15 A system level design methodology
The required transmission system comprises an 8 bit Analogue
to Digital Converter (ADC) interfacing to a parallel in/serial
out Transmitter Unit. The ADC is available as a standard discrete
component requiring an external clock and a positive edge
Start Conversion signal. The Transmitter Unit will be designed
as a digital system on an appropriate integrated circuit.
Analog input data will be sampled at a frequency of 16 kHz
and the ADC conversion time is 5 µs. Data will be transmitted
in serial byte format with a high start at the beginning of
the byte and a low stop bit at the end of the byte.
2) Define the Dataflow/Control Unit partition
Digital systems can be exclusively dataflow, control or a mixture of both. The first consideration here is to decide which of these is appropriate for the intended design. We know that the translation of parallel data to a serial bitstream will require data processing and that this activity will need to be controlled so both a dataflow unit and a control unit are necessary. We also need to make provision for the interface signals between these two units. At this stage the interface signals cannot be precisely defined until a detailed investigation of the dataflow requirements is undertaken. We can always assume, however, that the control unit will require both a system clock and a system reset and we know that a Start Conversion signal will be needed for the ADC.
Figure 16 Define the Dataflow/Control Unit Partition
3) Define the functional blocks for the Dataflow Unit
To define the functional blocks for the Dataflow Unit we need to consider the required operation of the unit. Depending on the depth of hierarchy in a design this may mean defining either further functional sub-blocks or macrofunctions. In a fairly simple design such as this we are now close to the primitive level so a consideration of suitable macrofunctions is appropriate. Dataflow circuitry can be exclusively combinational, sequential or a mixture of both. In this example we require the conversion of 8 bit parallel data to a serial bitstream with the insertion of appropriate start and stop bits. This suggests either a combinational approach using an 8 to 1 multiplexor macrofunction or a sequential approach using an 8 bit shift register macrofunction. We shall choose the shift register solution.
Figure 17 Define the functional blocks for the Dataflow Unit
To cater for the start and stop bit insertion the shift register will be extended to 9 stages, the first eight stages being loaded from the ADC and the ninth stage (effectively a D flip-flop) being loaded with a logic 1 to define the start bit. The serial input to the main shift register will be set to logic 0 to define the stop bit. We can now also define more of the interface signals. Each stage will require a system reset, a system clock and a shift/load signal. This latter signal will control the loading of a sample and its subsequent shifting out to form the output bitstream.
4) Define the functional blocks for the Control Unit
Control units in modern digital systems are invariably constructed from Finite State Machines using well defined procedures such as the Algorithmic State Machine (ASM) method. Both these are extensively covered in Unit 2 of this module. A state machine is basically a binary counter with combinational logic on its outputs to decode certain counts (states) and generate the required control signals. Additionally the counter steering logic will also have input signals originating from the dataflow. This is so that the count sequence can be altered in accordance with the status of the dataflow and different control signals generated. In this example there are no status signals feeding back from the dataflow so we can use a reduced form of state machine comprising just a counter and associated control signal logic.
Figure 18 Define the functional blocks for the Control Unit
The width of the counter will be determined by the number of states required in the count sequence. We know that we will need individual states to:
Generate a start conversion signal
Load the shift register
Shift a start bit
Shift 8 bits of data
Shift a stop bit
This implies 12 states so a 4 bit binary counter will be necessary.
The state sequence and associated control signals are as follows:
The ADC requires a positive going edge on the Start Conversion
signal to initiate a conversion. This will appear in state
0000.
Given a sampling frequency of 16 kHz and 16 states in the counter
the counter clock will need to be set at 16 x 16 kHz = 256
kHz,
giving a clock period of 3.9 µs. The specification defines
an ADC conversion time of 5 µs so we allow states 0000
and 0001 for the conversion to complete. The Shift/Load signal
performs the load operation when set to logic 0 and the shift
operation when set to logic 1. So the loading of data and start
bit occurs in state 0010. The remaining states define the shifting
operation. A reset will be required to initialise the system
to state 0000 and clear the shifter so during conversion the
shifter will be shifting out zeros (ie. the line will be set
low). In the states after the data has been shifted, zeros
again
are output (effectively copies of the stop bit) since we have
tied off the serial input of the shifter to logic 0.
The counter can be implemented by a suitable 4 bit binary counter macrofunction. The output logic will require primitive logic elements constructed using the techniques previously described for designing combinational macrofunctions. The state sequence defines the required truth table.
For example: Start Conversion = 
5) Implement the functional blocks in primitive functions/macrofunctions
The functional blocks for the Dataflow and Control Units can now be implemented using appropriate primitive functions/macrofunctions and combined together to define the final design. The following circuit uses library components from an Altera Programmable Logic Device design system to form the complete Transmitter Unit.
Figure 19 Implement the functional blocks in primitive functions/macrofunctions
Standard macrofunctions 7493 and 74166 have been utilised for the counter and shifter elements respectively. The shifter is extended to include the start bit with a D flip-flop. Note in particular the use of the Multiplexer element to load the start bit (Vcc on input B = logic 1) into this element or to connect the shifter output. This is to ensure that the design remains completely synchronous. This and other best practice techniques are dealt with in the main Unit 1 material.