Digital Integrated Circuit Design
Unit 1 - Best Practice Digital Design
Unit Contents
- 1.1 Introduction Digital Designers Guide
- 1.2 Digital Circuit Structures
- 1.3 Digital Library Components
- 1.4 Unused Inputs and Outputs
- 1.5 Fanouts and Loading
- 1.6 Buffering Strategies
- 1.7 System Resets
- 1.8 Local Resets
- 1.9 System Clocks
- 1.10 Local Clocks
- 1.11 Clocking Strategies
- 1.12 Delay Circuits
- 1.13 Spikes and Glitches
- 1.14 Level and Edge Triggered Devices
- 1.15 Summary
- 1.16 Self Assessment Questions
1.1 Introduction
Designing efficient, reliable, robust digital circuits requires adherence to the principles of good design practice. For the most part these are applicable regardless of whether the implementation is discrete or customised. Badly designed digital circuitry has a tendency to generate timing hazards such as spikes and glitches. Whilst a design may exhibit correct functionality many of the problems associated with poor reliability are attributed to the way in which these hazards are handled. It is vitally important that designs intended for implementation on ASICs must conform to all the accepted rules of best practice for digital design. Failure to do so can result in designs that are unsafe, difficult to test and whose operation cannot be guaranteed. Mask programmable devices in particular are high risk when attempting to achieve a right first time design. For this reason the silicon foundry will insist that the designer completes a sign-off form indicating compliance with all the foundry defined recommendations. In cases where non-compliance occurs these must be discussed with the foundry design centre and appropriate authorisation obtained before the design can be accepted. This unit reviews the principles of best practice and identifies any additional considerations that are specifically relevant to realisation on silicon.
It is assumed that the reader is already familar with the basic combinational and sequential logic elements and their use in the construction of standard digital functions. Digital design is rarely taught from the practical point of view. Some essential information that is certain to be relevant to everyone is contained in another page that we expect you will find useful throughout this module. Please refer to the Digital Designer's Guide now, before continuing with this unit.
1.2 Digital Circuit Structures
Digital circuits can be classified as comprising two distinct functional structures, dataflow and control. Dataflow elements process data whilst control elements define the manner in which this processing is performed. Designs can be exclusively dataflow or control but generally comprise a mix of both as shown below.
Figure 1.1 Digital Circuit Structures
Control elements provide Control and Status signals to and from the Dataflow. Control signals are generated from defined control sequences whilst Status signals are used to modify the flow of such sequences. Interface Signals are often needed to facilitate communication with other parts of the design or components external to the chip. Examples would be inputs from sensors, outputs to controlled elements, protocol signals such as Data Available & Data Accepted etc. The inclusion of sequential logic elements in Control Structures requires the provision of a system Clock to synchronise activity with the rest of the design and a general Reset to initialise the system to a known starting condition for both normal and test operating modes. Designing control elements is often the most difficult part of a digital system implementation. As designs have grown in size and complexity there has been a move towards replacing intuitive design techniques and resulting customised circuitry with more formal design methodologies and standardised design structures. The Finite State Machine is an example of a standard control structure implementation that can be designed by a technique known as the Algorithmic State Machine (ASM) method. Both these are comprehensively explained in Unit 2 of this module.
Dataflow elements input, logically manipulate and then output data. Typically they comprise arrangements of combinational and sequential logic components. Control signals are applied to move data through the dataflow in a specific way, eg. the add/subtract signal on an adder component whilst status signals provide information relating to specific conditions arising, eg. a zero value on a counter component. Dataflow design is generally less formalised than control but a number of standard structures exist for the main logic functions eg. adders, counters, shifters, multiplexors etc.
1.3 Digital Library Components
An ASIC designer will be provided with a Cell Library containing a variety of combinational and sequential logic components. These can be categorised as follows:
Primitive Components
These offer the lowest level of functionality, typically
AND, OR, NOT gates, FLIP-FLOPS etc. that are the basic elements
of logic circuits. The Mietec Standard Cell Library, for example,
comprises a large proportion of these elements. Click on a
category to see the components available.
| Category | Description |
|---|---|
| Simple Gates | Basic logic functions |
| Complex Gates | Basic logic combinations |
| Latches | Level triggered storage elements |
| Flip-Flops | Edge triggered storage elements |
Defining components at the primitive level provides a number of advantages:
- The flexibility to construct the random logic usually required around higher level functions.
- The ability to define non-standard components not available in the cell library. For example there will typically be a range of 4 bit and 8 bit counters in the library but no other bit lengths.
- The opportunity to define silicon efficient structures. For example a counter component from the cell library may have a load facility not required by the design. Utilising a primitive level implementation will not include this feature.
A primitive level circuit will generally provide the most
efficient implementation in terms of chip area and speed.
For this reason a logic synthesiser compiling down from a
high level functional language such as VHDL or Verilog will
tend to generate a primitive component implementation.
Designing manually with these components, however, will inevitably
lengthen the design time and increase the risk of design errors.
Macro Components
These are higher level functions, typically adders, comparators, multiplexors, counters, shifters etc. that are the basic functions of logic circuits. The Altera Programmable Logic Device library, for example, provides a comprehensive set of macro components.
Figure 1.2 Macro Components
Within each category there is a set of ASIC equivalent implementations for standard 74 series components as in the Decoder category shown below.
Figure 1.3 Decoder Macrofunctions
Defining components at the macro level provides a number of advantages:
- Shorter design times
- Guaranteed correct functionality by the ASIC vendor
- Easy migration to silicon of designs constructed from discrete standard components
A macro level circuit can be designed more quickly with less
potential for design errors but could be less efficient in
utilising silicon. Often there will be features available
on a macro component that are not required and will need to
be rendered inactive by tying off related inputs to the appropriate
logic levels.
Generated Components
A number of ASIC design systems incorporate a facility for generating user defined logic functions. These can range from customised macro components to high level functional blocks such as RAM (Random Access Memory), ROM (Read Only Memory) and PLA (Programmable Logic Array). The following is a Xilinx menu for generating a customised counter with various options for defining clock, reset, count direction, bit length etc.
Figure 1.4 Generated Components
Generated components offer the shortest design times and the most efficient utilisation of silicon area.
1.4 Unused Inputs and Outputs
Often when constructing a schematic for a digital circuit there will be component pins to which nothing needs to be connected, as in the flip-flop example below.
Figure 1.5 Unused Inputs and Outputs
There are specific connections for the D (Data), CLK (Clock), R (Reset) and Q pins but none required for the S (Set), EN (Enable) and NQ pins. The rules are as follows:
Unused Inputs
NEVER EVER LEAVE UNUSED INPUTS OPEN CIRCUIT. They must always be tied off to appropriate logic levels. Some ASIC topologies will have pull up/pull down devices within the component circuit, others will not. In both cases leaving an input open circuit will render it susceptible to picking up signals from adjacent metal tracking on the silicon causing the component to logically malfunction. An additional problem occurs with components that have no pull up/pull down devices. Since an input is now effectively floating it can assume either logic level making the operation of the component unpredictable.
At the silicon level an unused input will be connected to one or other of the power supply rails, power (VDD) for a logic 1 and ground (GND) for a logic 0. This is denoted on the schematic in one of two ways depending on the design system being used.
1) The cell library supplies symbols for the power supply levels. This method is illustrated on the EN input of the example.
2) The wire connecting to the component pin can be named with the appropriate power supply label. This method is illustrated on the S input in the example.
In all cases the correct logic level must be specified to
achieve the required logic functionality. In the example,
the EN input needs to be a logic 1 to enable the component
to function but the S input must be at logic 0 to avoid the
component set function being activated.
Unused Outputs
Unused outputs can be safely left open circuit as with the NQ output in the example but NEVER ATTEMPT TO CONNECT TWO OR MORE OUTPUTS TOGETHER. Inexperienced designers assume that this will provide an AND or an OR function. It simply shorts the outputs together producing an output voltage that corresponds to neither of the defined logic levels. Use the appropriate logic element for the function required.
1.5 Fanouts and Loading
Signals such as clocks and resets that are heavily loaded and other signals whose timing is critical need special attention. In TTL technologies increasing the loading on a signal results in a deterioration of the logic levels. In MOS the result is to add capacitance which slows down the edges, increases the potential for metastability (flip-flops capturing asynchronous data), introduces clock skew and can quickly turn a synchronous design into an asynchronous one. The effect is demonstrated below for a CMOS circuit containing both an unloaded and a loaded inverter.
Figure 1.6 Composer-Schematic Editing: inverter loadedlogic schematic
The unloaded device exhibits a small exponential edge deterioration on its output due to the charging and discharging of its intrinsic capacitance. The loaded device, however, drives the additional input capacitance of its load devices and their associated track interconnect and as such exhibits a much more pronounced effect.
Figure 1.7 Waveform Window
Logic simulators allow for this effect by calculating the overall propagation delay of a component with reference to additional delay data as in the example below.
| Cell Type | Transition | Unloaded Delay (ns) | Load Value | Delay/Unit Load (ns) | Loads | Track Delay (ns) | Total Delay (ns) |
|---|---|---|---|---|---|---|---|
| INVERTER | low - high | 1 | 1 | 0.4 | 6 | 0.1 | 3.5 |
| high - low | 0.7 | 1 | 0.25 | 6 | 0.1 | 2.3 |
The simulator performs the following calculation:
Total Delay (low - high) = Unloaded delay + ( Unit Loads
x Delay/Unit Loads x Loads) + Track Delay
= 1 ns + (1 x 0.4 ns x 6) + 0.1 ns
= 3.5 ns
Total Delay (high - low) = 0.7 ns + (1 x 0.25 ns x 6) + 0.1 ns = 2.3 ns
The Load Value indicates the loading effect a component input exerts on the output of another component from which it is being driven. Typically an inverter circuit is taken as the reference since it comprises the minimum number of transistors (1 PMOS and 1 NMOS) with the input signal connected to the gates of both devices. More complex functions will have higher load values. For example an EXCLUSIVE OR component implementing the function A'B + AB' as a complex gate will have a load value of 2, each input feeding 1 PMOS and 1 NMOS transistor in the AND/OR structure plus 1 PMOS and 1 NMOS transistor configured as a inverter to provide the NOT function. Thus in the example an inverter feeds 6 similar components so the loading is 6 x 1. If it were feeding 6 EXCLUSIVE OR gates the loading would be 6 x 2.
The Delay/Unit Load is a value provided by the silicon foundry, usually obtained from parametric testing of circuit samples.
The Loads figure is obtained from the schematic.
The Track Delay is obtained after layout has been completed so will not be present in design simulations but will be incorporated into a final post-layout simulation.
The simulator will indicate the effect of signal loading. Some CAD systems impose a limit on the number of loads that can be connected to a signal and check for this during the design process. Others leave it to the designer. A good rule of thumb is to limit the number of loads to10. Not only will this minimise timing hazards but will also assist the router during the layout process since a short length of interconnect is easier to route than a long one.
1.6 Buffering Strategies
To eliminate or minimise the effects of signal loading, designers should consider an appropriate signal buffering strategy both to equalise the load and provide increased drive capability.
Non-Recommended Buffering
Shown here are two examples of non-recommended buffering. In the left hand example some clock lines are buffered, others are not. Clock signals travelling through the buffered lines will be delayed relative to those that are not. Consequently some of the logic elements being fed from the circuit will receive the clock before others, an effect known as 'clock skew'.
In the right hand example unequal loading in the buffering circuit will again produce differential delays in the clock lines resulting in clock skew.
Figure 1.8 Non-Recommended Buffering
Recommended Buffering
A correctly designed buffering circuit will provide the same
depth of buffering in each line and the same fanout on all
buffers. This is known as Balanced Tree Buffering. Moreover,
in order to keep signal edges sharp buffers must be lightly
loaded. This arrangement is referred to as Geometric Tree
Buffering. Note, however, that even when these principles
have been applied at the circuit design stage, the layout
process can produce differing tracking capacitances which
will introduce imbalance into the fanout. For this reason
is it essential that a final post-layout simulation that includes
these additional delays is performed and the design timing
checked.
The circuit below shows an example of Balanced Tree Buffering in which all clock lines are equally loaded.
Figure 1.9 Recommended Buffering
1.7 System Resets
Designs implemented on ASICs are required to be brought to a known state within a given number of clock cycles. This is necessary both for normal operation where a circuit has to be initialised to a given starting condition and also during testing before a sequence of test patterns can be applied. The recommended method of achieving this is to apply an asynchronous system reset to all sequential elements in the circuit.
Recommended System Reset
Here an external system reset is applied via an input pin to the reset inputs of all sequential elements so that the entire circuit can be initialised simultaneously. The reset signal can be provided by an external power-on circuit or reset button or both. Alternatively some ASIC topologies provide a power-on reset peripheral pad specifically for this purpose. When this facility is used a separate reset must also be incorporated for test purposes since it is usually necessary to re-initialise the circuit several times during a test run.
Figure 1.10 Recommended System Reset
1.8 Local Resets
Synchronous designs are always recommended for implementation on ASICs. Any asynchronous operation immediately increases the potential for timing hazards and makes testing difficult. In situations where sections of sequential logic require a local reset this should always be done synchronously.
Non-Recommended Local Reset
The circuit below details a common technique employed to asynchronously reset sequential elements such as counters.
The circuit violates the rules of synchronous design. The second flip-flop can change state at a time other than the active clock edge. There is also a potential race condition between the clock and the reset of this flip-flop.
Figure 1.11 Non-Recommended Local Reset
Non-Recommended Local Reset
Similar problems occur when combinational logic is used to generate a reset. A common application of this design style is the use of decoding logic on the outputs of a counter.
Typically AND/OR gates will be used to detect a required state in the counting sequence and provide an asynchronous reset back to the counter reset inputs.
Figure 1.12 Non-Recommended Local Reset
Recommended Local Reset
The recommended alternative to providing asynchronous resets to these type of circuits is to clock the flip-flop to the required zero state. This effectively produces a synchronous reset.
In this circuit all flip-flops are synchronised to the clock. A reset required on the second flip-flop as a result of signal r going active will now occur on the next rising edge of the clock.
Figure 1.13 Recommended Local Reset
1.9 System Clocks
Great care has to be taken when handling clocks in sequential designs. Unwanted spikes, glitches, clipped pulse widths and additional clock pulses all provide potential for circuit failure. Feeding clocks into combinational logic for further processing causes no end of timing hazards. Here are two examples of this technique.
Non-Recommended Gated Clocks
In the left hand circuit the intention was probably to inhibit/enable
the clock. The en signal, however, arrives late at the AND
gate input and the result is an unwanted glitch.
In the right hand circuit the intention was to switch between ck1 and ck2. The ctrl signal occurring as it does clips the beginning of both clocks resulting in two unwanted glitches.
Figure 1.14 Non-Recommended Gated Clocks
There are many more effects that can occur depending on the state and timing of the signals involved. Furthermore the inclusion of combinational processing logic adds delay to the resultant signals resulting in variable amounts of clock skew. Now we have a situation where the sequential elements in the circuit are being clocked at differing times relative to the initial master clock.
Recommended Gated Clocks
In circumstances where clocks have to be gated with enable signals the use of a sequential element with a built-in enable input is recommended. If this is not available the circuit opposite achieves the same functionality.
In this arrangement the gating function previously provided by the AND gate is now implemented by the multiplexor. The circuit, however, is now completely synchronous with the master clock feeding directly into the flip-flop. With the enable signal en set low the current state of the flip-flop is retained on a rising clock edge; with en set high new data is loaded.
Figure 1.15 Recommended Gated Clocks
1.10 Local Clocks
As with resets it is possible to generate asynchronous clock signals from sections of sequential logic and these can violate the principles of synchronous design.
Non-Recommended Local Clocks
A common technique in counter design is to generate a clock
from the output transition of another sequential element.
The following ripple counter provides an example in which
a generated clock from one stage implements a toggle function
in the next. The second flip-flop is clocked only when the
first flip-flop changes from a logic 1 to a logic 0.
There are two problems with this arrangement. The generated clock to the second flip-flop is skewed by the clock-to-q propagation delay of the first flip-flop and also the second flip-flop cannot be clocked on every edge of the master clock. Again this will cause problems with testing methodologies.
Figure 1.16 Non-Recommended Local Clocks
Recommended Local Clocks
The circuit below provides the equivalent function. Again the circuit is fully synchronous. When the toggle input is low the flip-flop retains its current state; when the toggle input is high the flip-flop assumes its opposite state.
In counter design the toggle input can be provided from the q output of the previous stage flip-flop.
Figure 1.17 Non-Recommended Local Clocks
1.11 Clocking Strategies
When speed is critical in a digital system, designers often resort to dubious clocking strategies in an effort to maximise performance. An apparently attractive technique for increasing the rate of data throughput in a circuit is that of Double Edged Clocking in which flip-flops in a circuit can be clocked on either the rising or falling edge of the clock.
Non-Recommended Strategy
The circuit below shows a first flip-flop activated by the true version of the clock whilst an inverter feeds a second flip-flop elsewhere in the circuit with an inverted version.
Both devices are sensitive to rising clock edges but the overall effect is to clock the first flip-flop at the beginning of the clock pulse and the second at the end.
Figure 1.18 Non-Recommended Strategy
The problems with employing this kind of technique relate to synchronous resetting, set up and hold time violations, determination of critical paths and implementation of test methodologies. Synchronous resetting (ie. where flip-flops are reset on the coincident occurrence of a clock edge and a reset signal) is impossible since not all devices are clocked on the same edge. Set up times (ie. the time before a clock edge that data has to be present) and hold times (ie. the time after a clock edge that data has to remain) are in danger of being violated as timing becomes finely tuned. Critical delay paths through the circuit are difficult to assess with multiple timing regimes present. Test methodologies such as scan path in which patterns are inserted into a circuit via its flip-flop elements are impossible again because all flip-flops have to be clocked at the same time.
In general this technique rarely works well in a design. Attempts to 'borrow time' in one part of a circuit often result in complications occurring somewhere else. A better solution is to use a single edged clocking scheme with a higher clock frequency.
Non-Recommended Strategy
Similar problems occur when double edged clocking techniques are used in more formal design arrangements. This circuit details a pipelined structure in which data from a first storage level is processed by combinational logic for subsequent transmission to a second storage level.
The arrangement suggests a design that is very 'edgy'. Any increase, for example in the propagation delays of the combinational logic, could result in circuit failure.
Figure 1.19 Non-Recommended Strategy
Recommended Strategy
Again a better solution is to revert back to a single edged clocking scheme as shown opposite.
The circuit is clocked at twice the frequency of the double edged version to achieve the same throughput.
Figure 1.20 Recommended Strategy
1.12 Delay Circuits
Digital designers often utilise logic components such as inverters and buffers to achieve some required delay and assume that this can be done on ASICs. Examples include the adding of delays in combinational circuitry to equalise propagation delays and remove glitches or the delaying of a clock edge to a flip-flop in order to allow more time for the data input to settle. It is also tempting to try and reproduce the functionality of pulse generators, monostables and multivibrators on silicon using delay elements. These practices are not generally recommended. The delay of any logic component on an ASIC cannot be guaranteed. It will vary with temperature, power supply voltage and different fabrication runs. Logic simulators enable the effects of these variations to be observed by allowing the simulation to be implemented at minimum, typical and maximum operating conditions. Typical refers to nominal operating temperature and power supply voltage. Minimum will multiply all the component delays on the chip by a scaling factor of around 0.5 to define the shortest circuit delays whilst maximum will use a factor of around 1.5 to define the longest delays. In this way the designer can tolerance the circuit over the entire operating range of the fabrication process. A good design will be stable throughout. A bad design that passed a simulation under typical conditions is likely to fail at this point when the variable delays move timing hazards into contention.
Non-Recommended Pulse Generator
The circuit below uses inverters to implement a delay on the Input Trigger signal. The settled state with this signal set low produces a logic 1 on the top input to the AND gate, a logic 0 on the bottom input and a logic 0 on the Pulse output. When the Input Trigger goes high both inputs to the AND gate will be momentarily high, producing a logic 1 on the Pulse output. After a time equal to the propagation delay of the delay line the top input of the AND gate will go low and the pulse is terminated.
The main problem with this circuit is that variations in the inverter delays previously described will affect the width of the output pulse and this cannot now be consistently guaranteed.
Figure 1.21 Non-Recommended Pulse Generator
Non-Recommended Pulse Generator
Here the delay components are used in the feedback path of
a flip-flop to control an active low reset input. In the stable
state the flip-flop will be reset and the Pulse signal will
be set low. Upon the application of a positive going clock
edge the q output of the flip-flop will assume the logic 1
state, setting the Pulse signal high. The qb output will assume
the logic 0 state. This will ultimately propagate through
the inverters resetting the flip-flop and producing
a pulse on the q output equal in width to the delay through
the delay components.
As in the previous circuit the problem with this kind of arrangement is the difficulty in maintaining a consistent pulse width with varying component delays.
Figure 1.22 Non-Recommended Pulse Generator
There are also fundamental design deficiencies with the circuit. There is no independent external reset to the flip-flop so the initial state of the output at switch-on is unpredictable. It could be a logic 0 or it could be a logic 1. The circuit can neither be simulated during the design phase nor tested during manufacture. The simulator will not be able to predict the state of the output at time t=0 (ie. at power-on) and will display this as indeterminate. This condition will be propagated throughout the entire simulation since the simulator requires a known initial state to predict all subsequent states. Likewise a tester will require all flip-flops to be set to a known initial state before the test patterns are applied so that the comparison between expected and captured output values is valid. A design sign-off at the foundry cannot therefore take place.
In practice, however, the circuit will assume a stable state on power-on. Should the Pulse output be a logic 0 the qb output of the flip-flop will be a logic 1, the reset feedback signal r will be an inactive logic 1 and the flip-flop will remain in its present state. If on the other hand the Pulse output is a logic 1 on power up, r will ultimately settle to a logic 0 after the qb has propagated through the delay line, the flip-flop will reset and the Pulse output will assume a logic 0. Two effects relating to the operation of the circuit should be noted. Firstly, if the power-on condition is this second case (the Pulse output is a logic 1 on power-up) a negative going edge will be generated on the Pulse output. This could be serious if this signal is being used as a clock to some other sequential logic. Secondly since the circuit has no reset that could be applied externally from a pin on the chip (eg. from a system reset button or power-up circuit) there is no way of re-initialising the design should it hang up during operation.
Non-Recommended Multivibrator
This circuit uses a delay line to produce a series of pulses
controlled by a trigger input. The stable state is when the
Trigger signal is low, the top input to the AND gate is high
and the output is a logic 0. When the Trigger input goes high
the output will go momentarily to a logic 1 until this value
works its way through the delay line to produce a logic 0
on the top input of the AND gate and the pulse terminates.
The whole cycle repeats itself for as long as the Trigger
signal is active.
Again the problem with this circuit is the width of the monostable pulses and their proportionality to the inverter delays.
Figure 1.23 Non-Recommended Multivibrator
Recommended Pulse Generator
The following circuit utilises synchronous techniques to ensure a consistent pulse width synchronised to the clock period. Assuming that a reset has occurred, the q output of the first flip will be logic 0 whilst the qb output of the second flip-flop will be logic 1 and the pulse output from the AND gate will be low.
When the trigger input is high and a rising edge occurs on the clock input ck, the first flip-flop will go high whilst the second will take on the state of the first before the clock edge occurred ie. a logic 0. Hence its qb output will be logic 1 and with both inputs of the AND gate at this value its pulse output will go high. On the next rising edge of the clock if the trig input is now low the first flip will go low, the second will set high with its qb output low and the pulse output of the AND gate returns to logic 0.
Figure 1.24 Recommended Pulse Generator
1.13 Spikes and Glitches
Many designers viewing simulation output results for the first time are horrified to see spikes and glitches in waveforms. Even after adherence to the principles of best practice there will still be many occasions when these hazards occur. Each time a logic circuit is clocked, a new state is defined and this will require time to settle as the various propagation delays through the logic expire. During this unstable period there could be all manner of hazards. The principles of synchronous design are devised such that none of this activity is coincident with a clock edge and cannot therefore affect the intended operation of the circuit.
Figure 1.25 Spikes and Glitches
Circuit Instability
A positive going edge on a clock signal causes a change in the value of a count signal somewhere in the circuit. After an initial delay td when the circuit propagation delays start to take effect this signal will begin to change. There then follows a period of instability until all propagation delays have expired. None of this instability can effect the operation of the circuit since it occurs after the clock edge. The signal remains in a stable state for a period of time ts until the next clock edge, after which another change of state occurs.
Two conditions are relevant to the successful operation of this arrangement.
1) A signal being fed to the data input of a flip-flop must be settled before the Setup Time of the flip-flop. Any change after this time can store an incorrect value.
2) A signal being fed back from the output of a flip-flop directly or through logic to its input must not change state within the Hold Time of the flip-flop. If this occurs the new value will overwrite the current value.
1.14 Level and Edge Triggered Devices
Hazards in digital circuits can also be generated and propagated by the wrong choice of flip-flops. In most cases this relates to the use of level triggered rather than edge triggered devices. In a level triggered flip-flop the state of the data input is captured throughout the whole time the clock is active.
Figure 1.26 Level and Edge Triggered Devices
Generated Hazard
The circuit below details a level triggered device utilised in a feedback loop. This is a common arrangement in processor design where, for example, a register may feed into an adder and back to itself. When the clock input goes active the combinational logic processes the state of the flip-flop output and feeds back a new value to the data input. If this new value is different from the old value the flip-flop changes state, presenting this new value to the combinational logic for further processing.
The whole activity repeats itself continually until the clock input goes inactive, generating an oscillating signal known as a Race Condition
Figure 1.27 Generated Hazard
Propagated Hazard
In this circuit a level triggered device is used to capture data from the output of combinational logic which has generated hazards due to varying propagation delays in its circuitry. When the clock input goes active the current state of the flip-flop data input is captured and presented to the output. Some time later the data input changes to a new value and again this is transmitted to the output.
During the time that the clock is active the flip-flop is performing the function of a Transparent Latch whereby any change in input value is immediately transferred to the output. In this way an unstable input signal presented to the flip-flop will be propagated to other circuitry fed by its output.
Both of these types of hazard can be eliminated by replacing the level triggered devices with edge triggered devices. Now the input data will be captured only on a clock edge so any variation in the data input of the device will not be transmitted to the output. As a general rule it is always wisest to use edge triggered devices in synchronous designs. Typically level triggered schematic symbols are characterised by having a box adjacent to the clock pin whilst edge triggered devices employ a chevron.
1.15 Summary
The following summarises the rules of best practice for digital design
- Keep designs synchronous
- Use edge triggered devices
- Tie off all unused inputs
- Avoid the use of components as delays
- Avoid gating clocks
- Avoid double edge clocking strategies
- Always provide a system reset
- Power up heavily loaded and critical signals
- Simulate rigorously before and after layout
- Adhere to the ASIC foundry's recommendations
Self Assessment Questions
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