Advanced Microelectronics for Industrialists
Mietec 2 Micron Cell Data
Digital Core Cells - Simple Gates
| Cell Name | Functional Description |
|---|---|
| INV 1 | Inverter |
| INV2 | Inverter (x2 drive) |
| INV4 | Inverter (x4 drive) |
| INV8 | Inverter (x8 drive) |
| NAND2 | 2-input nand |
| NAND3 | 3-input nand |
| NAND4 | 4-input nand |
| NAND5 | 5-input nand |
| NOR2 | 2-input nor |
| NOR3 | 3-input nor |
| NOR4 | 4-inport nor |
| NOR5 | 5-input nor |
| BUF2 | Buffer (x2 drive) |
| BUF4 | Buffer (x4 drive) |
| BUF8 | Buffer (x8 drive) |
| BUF13 | Buffer (x13 drive) |
| BUF20 | Buffer (x20 drive) |
| AND2 | 2-input and |
| AND3 | 3-input and |
| AND4 | 4-input and |
| AND6 | 6-input and |
| AND7 | 7-input and |
| AND8 | 8-input and |
| OR2 | 2-input or |
| OR3 | 3-input or |
| OR4 | 4-input or |
| OR6 | 6-input or |
| OR7 | 7 input or |
| OR8 | 8-input or |
Digital Core Cells - Complex Gates
| Cell Name | Functional Description |
|---|---|
| EXOR | 2-input exor |
| EXNOR | 2-input exnor |
| ANDNOR | 2x2-input and-nor |
| ORNAND | 2x2-input or-nand |
| TRIINV1 | Tristate inverter |
| TRIBUF | Trisate non-inverter buffer |
| MUX21 | 2 to 1 multiplexer with inverting output |
| MUX41S | 4 to 1 multiplexer with inverting output |
| MUX2 | 2 to 1 multiplexer with non-inverting output |
| DEC2E | 1-line to 2-line decoder with enable |
| DEC4E | 2-line to 4-line decoder with enable |
| HALFA | Half adder |
| FULLA | Full adder |
Digital Core Cells - Latches
| Cell Name | Functional Description |
|---|---|
| DL | D-latch (active if EN is high) |
| DLL | D-latch (active if ENB is low) |
| DLRL | D-latch with reset (active low) |
| DLRLPU | D-latch with reset (active low) and D-input connected to VDD |
| DLSL | D-latch with set (active low) |
| DLSLO | D-latch with set (active low and Q-output only) |
| DLSLQB | D-latch with set (active low) and QB-output only) |
| DLSHRL | D-latch with set (active high) and reset (active low) with reset dominant |
Digital Core Cells - Flipflops
| Cell Name | Functional Description |
|---|---|
| DFFRL | Positive-edge triggered D-flipflop with asynchronous reset (active low) |
| DFFP | D-flipflop with present |
| DFFRL | Positive-edge triggered D-flipflop with asynchronous reset (active low) |
| DFFRLPU | Positive-edge triggered D-flipflop with asynchronous reset (active low) and D-input connected to VDD |
| DFFSRLQ | Positive-edge triggered D-flipflop with synchronous reset (active low) and Q-output only |
| DFFSRLOB | Positve-edge triggered D-flipflop with synchronous reset (active low) and QB-ouput only |
| DFFSL | Positive-edge triggered D-flipflop with asynchronous set (active low) |
| DFFSLRL | Positive-edge triggered D-flipflop with asynchronous set and reset (both active low) |
| SCDSRLQ | Positive-edge triggered SCAN-D-flipflop with synchronous reset (active low) and Q-output only |