Unit 1 - Best Practice Digital Design

Self Assessment Questions

Question 1

The circuit shown below has been designed to provide a pseudo random number sequence as follows: A B C D
0 0 0 0
1 0 0 0
0 1 0 0
1 0 1 0
0 1 0 1
0 0 1 0
1 0 0 1
1 1 0 0
0 1 1 0
1 0 1 1
1 1 0 1
1 1 1 0
0 1 1 1
0 0 1 1
0 0 0 1
0 0 0 0

To guard against the sequencer inadvertently assuming the illegal lock-up state of 1111, a circuit reset is provided.

What

Would the output of a simulator show for the state of flip-flops ABCD after the fourth clock pulse?

The circuit contains no means of exerting an external reset so the simulator will show the output as indeterminate for the entire length of the simulation.

Question 2

The circuit contains a number of design violations. How many can you detect?

No external global reset
Reset circuitry provides wrong phase of signal
Reset is asynchronous
Flip-flop set inputs left open circuit
Flip-flops are level triggered, not edge triggered
Clock signal is double edged (wrong sequence will result)
Clock signal is skewed

Question 3

Propose suitable modifications to the circuit to satisfy the foundry design regulations and provide the correct functionality.