Digital Integrated Circuit Design
Unit 2 - Answer to Design Exercise
ASM Chart
NR = North-South Red
EW = East-West Red etc.
SC = SPOT_CTRL
SPOTS = SPOTLIGHTS
Figure 1 ASM Chart
AU = AUTO
Figure 2 State Assignments
Figure 3 ASM Table
Figure 4 Logic Synthesis
Similarly for NR, NA, NG, ER ,EA , EG and SPOTS
Figure 5
VHDL Code
library IEEE;
use IEEE.std_logic_1164.all;
entity TLIGHT_CTRL is
port (CLK, RESET, AU, SC : in std_logic;
SPOTS, NR, NA, NG,ER, EA,EG :out
std_logic);
end TLIGHT_CTRL;
architecture BEHAVIOUR of TLIGHT_CTRL is
type STATE_TYPE is (ONE,TWO,THREE,FOUR,FIVE,SIX,SEVEN,EIGHT);
signal STATE: STATE_TYPE;
begin
FSM : process (CLK, RESET)
begin
if RESET = '1' then
STATE <= ONE;
elsif CLK'event and CLK ='1' then
case STATE is
when ONE =>
if
AU = '0' then
STATE <= ONE;
elsif
AU = '1' then
STATE <= TWO;
end
if;
when TWO =>
STATE
<= THREE;
when THREE =>
STATE
<= FOUR;
when FOUR =>
STATE
<= FIVE;
when FIVE =>
if
AU = '0' then
STATE <= FIVE;
elsif
AU = '1' then
STATE <= SIX;
end
if;
when SIX =>
STATE
<= SEVEN;
when SEVEN=>
STATE
<= EIGHT;
when EIGHT =>
STATE
<= ONE;
end case;
end if;
end process FSM;
SPOTS <= '1' when (STATE = ONE) and (AU = '0') and
(SC = '1') else
'1' when (STATE = FIVE) and (AU = '0' ) and (SC = '1') else
'0';
NR <= '1'
when (STATE = ONE) else
'1' when (STATE = TWO) else
'1' when (STATE = FIVE) else
'1' when (STATE = SIX) else
'1' when (STATE = SEVEN) else
'1' when (STATE = EIGHT) else '0';
NA <= '1'
when (STATE = TWO) else
'1' when (STATE = FOUR) else'0';
NG <= '1'
when (STATE = THREE) else '0';
ER <= '1'
when (STATE = ONE) else
'1' when (STATE = TWO) else
'1' when (STATE = THREE ) else
'1' when (STATE = FOUR) else
'1' when (STATE = FIVE) else
'1' when (STATE = SIX) else '0';
EA <= '1'
when (STATE = SIX) else
'1' when (STATE = EIGHT) else'0';
EG <= '1'
when (STATE = SEVEN) else '0';
end BEHAVIOUR;
configuration CONFIG_TLIGHT_CTRL of TLIGHT_CTRL is
for BEHAVIOUR
end for;
end CONFIG_TLIGHT_CTRL;