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Digital Integrated Circuit Design

Standard Cell Design Walkthrough 1
Entry and Simulation of Standard Library Components

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Contents

• Walkthrough Overview
• Conventions Used in this Walkthrough
• Creating a Design Directory
• SCHEMATIC ENTRY
• Introduction
• Starting CADENCE
• Creating the Design Database
• Entering the Schematic
• Entering the Logic Components
• Entering the Input/Output Pins
• Wiring the Components
• Checking and Saving the Design
• GATE LEVEL SIMULATION
• Introduction
• Starting Verilog Simulator
• Creating a Stimulus Testfixture Template
• Creating Testfixture File
• Editing the Testfixture File
• Initialising and running the Verilog Simulator
• Displaying the Simulation Results
• Determining the Circuit Delays
• Leaving Cadence

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Walkthrough Overview

This walkthrough details the design flow for the schematic entry and simulation of a stepper motor driver circuit using components taken from the MIETEC 2 micron standard cell library.

The design flow uses the CADENCE tools Composer for schematic entry and Verilog for gate level simulation.The MIETEC design kit provides the component symbols for schematic entry and the functional models for the simulation.

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Conventions Used In This Walkthrough

1)    All commands typed at operating system prompts should be terminated with the RETURN key.
       Unix commands must be entered in lower case unless otherwise stated.

2)    Operations involving the mouse will use the left hand mouse button unless otherwise stated.

3)    Options selected from sub menus will be indicated as :-

       Main Menu option - Sub menu Option - Sub Menu Option

        E.g. File - New - Library

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Creating a Design Directory

Before beginning the design walkthrough it is necessary to create a design directory within your account for the design files.

Open up a UNIX terminal window

Type the following commands against the UNIX prompt terminating each with the RETURN key :-

mkdir stdcell                    [Create a directory named stdcell ]

cd stdcell                         [Move into directory stdcell]

mkdir smotor                   [Create a sub-directory smotor]

cd smotor                        [Move into sub-directory smotor]

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SCHEMATIC ENTRY

Introduction

This section details the operating instructions for invoking CADENCE and running Composer to enter the stepper motor driver schematic.

Instructions are provided for entering logic components, input/output pins and wires and for checking and saving the design.

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Starting CADENCE

Start the CADENCE design system with the MIETEC design kit by typing the following command at the UNIX  prompt and terminated by the RETURN key :-

cadence   -mietec      [Pay particular attention to the use of spaces]

After a short delay the CADENCE Command Interpreter Window (CIW) as shown below will appear. The window provides a tool bar for the top level menu commands and a display window for status information.

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Creating the Design Database

CADENCE defines a design database as a series of libraries, some containing components supplied by the device manufacturer (e.g. AND gates, FLIP FLOPS etc. ) and some generated by the designer. These components are referred to as cells. Our design will define a library called smotor and a cell called driver.

To define the library select File - New -  Library from the CIW
The New Library form shown below will be displayed

Click in the Name box and enter the library name smotor.

Ensure that the "Attach to an Existing techfile" button is activated

The completed form should be as shown above with your own design directory pathname in the bottom box.

Accept the form by clicking on OK.

When a library is created for the first time the Attach Design Library form will appear with the MIETEC mie24TechLib library selected as shown below :-

To define the cell select File - New -  Cellview from the CIW
The Create New File form shown below will be displayed

Click in the Library Name box and scroll down the list of libraries to select smotor

Click in the Cell Name box and enter the cell name driver

Click in the Tool box and scroll down the list of tools to select Composer-Schematic

Check that the View Name has automatically been entered as Schematic and that the form now appears as shown above.

Accept the form by clicking on OK.

The Composer-Schematic Editing window will now appear. This can be enlarged to full size if required by clicking on the square icon at the top right of the window.

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Entering the Schematic

The schematic window displays the main options along the top and a subset of these options in icon form down the left hand side.

The circuit schematic shown below will be assembled in three stages :-

1. Enter the logic components
2. Enter the input and output pins
3. Wire up the logic components and input/output pins

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Entering the Logic Components

Select Add - Instance ( or use the i key on the keyboard) to display the MIETEC Design Kit Library Menu as shown below.

Click in the scroll box immediately to the right of the Library Name box and select mie24Lib from the list of libraries.

Additional menus will now be added to the form. You may need to enlarge this form vertically and horizontally by pressing and holding down the left hand mouse button on the bottom right hand corner of the window whilst dragging the mouse to the new required position.

Click in the Digital Box to display the categories of standard cell digital components.The form should now be as shown below

Click in the FlipFlops box to display the list of available flip-flops and select DFFSLRL from the list..

The DFFSLRL component will now be attached to the cursor in the schematic window.
At this point you may wish to move the Design Kit Library Menu out of the way to faciltate the placement of the component. Simply press and hold down the left hand mouse button in the window title bar and drag to the required location.

Now position the component where required in the schematic window and click the left hand mouse button to fix in the required location.

Press the Esc key to terminate the Add Instance option and release the component from the cursor.

It may also be necessary to zoom out the display before placing further components.
Select Window - Zoom Out By 2 from the schematic window menu repeatedly until the required display size is achieved.
You may wish to use the keys [ and ] to zoom in and out more quickly.

Place another three instances of the DFFSLRL component.
This can be done in any of the following ways:-

• Repeat the Add Instance procedure as detailed above for each instance
• Select Add Instance mode but when a component has been selected and placed simply re-position the cursor to the required position for another instance and place by clicking the mouse button.When all instances have been placed termimate the option using the Esc key.
• Copy an existing instance by selecting Edit - Copy (or the c key) and clicking on the component to be copied. A copy of the component attached to the cursor will highlight. Position the component in the required location for the copy and click again to fix in position. Terminate the option using the Esc key.

Helpful hints for using the Schematic Entry package :

The Esc key will generally allow you to escape from any operation that has been incorrectly specified.

CADENCE provides operating instructions at the bottom of the schematic window for each selected operation.
 

As the component entry proceeds it may be necessary to move and delete components if mistakes are made. Before continuing we will practice moving and deleting one of the DFFSLRL components.

Move the component by selecting Edit - Move (or M on the keyboard) and clicking on the component to be moved. The component attached to the cursor will highlight. Position the component in the required new location and click again to fix in position. Terminate the option using the Esc key

Delete the component by selecting Edit - Delete ( or the Delete key) and clicking on the component to be deleted. The component will now be removed. Terminate the option using the Esc key

Restore the component by selecting Edit - Undo (or the u key). The undo command effectively cancels the last operation.

Now place the remaining components using EXNOR from the Complex Gates list for the Exclusive NOR elements and INV from the Simple Gates list for the inverter. Select the VDD component from the Miscellaneous List to define the inactive tie off level for the unused flip-flop sets and resets.

The schematic should now be as shown below

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Entering the Input/Output Pins

The input and output pins are defined as follows :-

Signal Name	Type	Function
reset	input	driver reset
dir	input	forwards/backwards select
clk	input	driver clock
a	output	motor winding a
b	output	motor winding b
c	output	motor winding c
d	output	motor winding d

Zoom into the area surrounding the inverter by selecting Window - Zoom In (or the z key). Position the cursor at the top left of the zoom area and press and hold the left hand mouse button. Drag the cursor to the bottom right of the zoom area and release the mouse button. The selected area will now be enlarged.

At any time you can revert to the full window view by selecting Window - Fit (or the f key).

Now select Add - Pin (or the p key) to display the Add Pin form as shown below.

Enter the pin name reset into the Pin Names box and terminate the input by pressing the RETURN key. An input pin symbol will now be attached to the cursor. Locate the pin in line with the inverter input as detailed in the circuit diagram at the beginning of the walkthrough and click to fix in position.Check that the pin name is displayed adjacent to the pin as shown below.

Repeat the procedure for the dir and clk input pins referring to the circuit diagram (dir connects to the top Exclusive NOR gate and clk to the clock input of each flip-flop)

Note: Input/Output pins can be deleted and moved using the same procedure as for components.

Follow the same procedure for the output pins referring to the circuit diagram (pin a connects to the top flip-flop output and pins b, c and d follow down in sequence)

Note: Before entering the pin name click on theDirection box and select output from the pull down menu

At this stage you may want to reposition some or all of the components. This is most easily accomplished by using the group move facility.

Select Edit - Move (or the M key).

Position the cursor at the top left hand corner of the group of components to be moved. Press and hold down the left hand mouse button and drag the cursor to the bottom right hand corner of the group. A yellow box will appear encompassing the components. Release the mouse button and all the components will highlight in white indicating that all have been selected. Click anywhere in the group to define a reference point and move the group to the new position. Click again to fix in the required location.

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Wiring the Components

There are two methods of connecting components depending on their relative positions.

1)    Automatic Connection

The connection between the input pin reset and the inverter is an example.

Select Add - Wire (narrow) or the w key.

Click on the input pin named reset to define the wire source. The wire will now be attached to the cursor. Click on the input terminal of the inverter to establish the wire destination and the wire will now be connected.
 

2)    Manual Connection

The connection between the output of the inverter just connected and the reset input of the bottom flip-flop is an example.

Click on the output terminal of the inverter and guide the wire by clicking on each required horizontal/vertical turning point until the wire destination is reached.

Repeat for the remainder of the wires as detailed in the circuit diagram

Cancel the Add Wire operation when you have completed all the connections by pressing the Esc key.

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Checking and Saving the Design

The design must be checked for schematic errors before saving in the database.

Select Design - Check and Save (or the X key).

Inspect the CIW for any errors and warnings that may have been reported. Expect four warnings relating to the unconnected inverse outputs of the flip-flops. These will flash on the schematic but can safely be ignored.

Errors however must be corrected. As for warnings the offending components or wires will be highlighted on the schematic for reference. Correct the errors and repeat the Check and Save operation until the schematic is error free.
 

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GATE LEVEL SIMULATION

Introduction

This section details instructions to simulate the driver circuit.

Instructions are provided to create a testfixture file for the simulation test vectors, run the Verilog simulator and display graphically the output results.

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Starting the Verilog Simulator

Select Tools - Simulation - Verilog XL from the schematic window.

The Setup Environment form which creates a simulation run directory will be displayed.

Check that the entries are as shown above and OK the form

The Verilog-XL Integration Control window will now be displayed.

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Creating a Stimulus Testfixture Template

A stimulus testfixture template can be generated from the schematic

Select Stimulus - Verilog from the Verilog-XL Integration Control window.

When a testfixture template is produced for the first time a window displays the message :-

"There is no testfixture in this run directory"

Select Yes to create the testfixture template.

The Stimulus Options form will now appear.

The testfixture template file testfixture.verilog will be displayed in the file list.

Click on the file name testfixture.verilog in the list to enter it into the File Name box then click the Apply Button

Verify that the Current Test Fixture box now specifies testfixture.verilog

Click on the View File button to open up a view window and display the file contents as shown below.
 

 // Verilog stimulus file.
// Please do not create a module in this file.
 

// Default verilog stimulus.

initial
begin
    clk = 1'b0;
    dir = 1'b0;
    reset = 1'b0;
end

The file defines the input & output signals and their type [1'b0 indicates a single wire signal]

Select File - Close Window from the View window to close the window.

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Creating the Testfixture File

The testfixture template is copied to a testfixture file to which will be added the required test vectors.

Click on the Copy button on the Stimulus Options form. The form may require enlarging vertically.

Ensure that the File Name box in the Copy From section is set to testfixture.verilog and the File Namebox in the Copy To section is set to testfixture.new

Click on the "Make Current Test Fixture" button then click Apply
Scroll up the file list to verify that testfixture.new has been created.

Click on the Select button and verify that testfixture.new has been entered into the File Name box.

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Editing the Testfixture File

The test vectors can be added to the textfixture file using the system editor.

Click on the Editbutton on the Stimulus Options form then select OK

An edit window will open displaying a copy of the testfixture template.

Add the following stimulus data so that the file contents are as shown below.

// Verilog stimulus file.
// Please do not create a module in this file.

// Default verilog stimulus.

initial
begin
    clk = 1'b0;
    dir = 1'b0;
    reset = 1'b0;
end

always #50000 clk = ~clk;

initial
begin
dir=0; reset=0;
#100000 reset=1;
#100000 reset=0;
#500000 dir=1;
#500000 $finish;
end
 

Explanation of the stimulus declarations

(Note: for the mietec technology all timings are in ps)

always #50000 clock=~clock;  - Defines a clock with a 50 ns toggle rate [i.e. a clock period of 100 ns]

dir=0; reset=0;  - Sets the specified signals to their initial logic values

#100000 reset =1; - Sets the reset signal to logic 1 at 100ns after the start of simulation
#100000 reset =0; - then logic 0 at100ns later.

#500000 dir=1; - Run the simulation for 500ns then set dir to logic 1

#500000 $finish; - Stops the simulation 500 ns later.

The initial declarations are used to set time to zero before each new set of data.
 

Select File - Save from the editor window to save the file contents.

(The editor window can be closed by selecting File - Close but it is recommended that it is left open for the moment in case modifications are required to the file).

Click on the Select button on the Stimulus Options form to define textfixture.new as the stimulus file and select OK

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Initialising and Running the Verilog Simulator

The simulator displays a large amount of delay information for each component in the circuit. This considerably slows down the simulation and is unnecessary at this stage in the design flow.

To disable this option select Setup - Simulation from the Verilog-XL Integration Control window to display the Simulation Options form. Enlarge vertically if necessary.

Click on the More box at the bottom of the form and enlarge the form vertically until the Other Options box is visible.

Click in this box after the +dlverbose option and use the backspace key to remove this option. This part of the form should now be as shown below.

Select OK to accept the change of option.
Note: This modification is required only once for each cellview in the design

Select Simulation - Start Interactive [or the Start Interactive icon, top left] in the Verllog-XL Integration Control window.

Status information will be displayed terminated by the C1> prompt at the bottom of the window.

Check this information for any reported errors. Correct in the testfixture file and restart the simulator.

You may get a message requesting a renetlist of the design. Respond by clicking No.
This would only be necessary if the schematic had been changed.

Select Simulation - Continue [or the Continue icon - second right from top] from the Verilog-XL Integration Control Window to run the simulator.

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Displaying the Simulation Results

Select Debug - Utilities - View Waveform (or the View Waveforms icon at the bottom right of the icon strip) from the Verilog-XL Integration Control menu.

After a short delay the DAI Signalscan Waveform window will open as shown below.

Before the simulation results can be displayed it will be necessary to select the required signals for viewing

Select DesBrows:1 from the top toolbar to display the DAI Signalscan Design Browser
Locate the Instances in Current Context column
Click on the test entry to reveal the next level down in the hierarchy which will be top
Click on the top entry and observe the contents of the Node/Variables in Current Context column

The following signals should be listed (your order may vary) :-
a
b
c
clk
d
dir
reset

Click on each of these in turn in the order you wish to have them displayed
Check that they are now listed in the left hand column ready for display as shown below.

Now select AddToWave from the DAI Signalscan Design Browser
The selected signals will now be displayed in the DAI Signalscan Waveform window

In order to see the complete simulation it will be necessary to select ZmOutXFull from the top toolbar

The display should now be as shown below.

Inspect the waveforms to verify that the circuit is functioning correctly according to the following sequence

reset	dir	a b c d	reset	dir	a b c d
1	X	1 0 1 0	1	X	1 0 1 0
0	0	0 1 1 0	0	1	1 0 0 1
0	0	0 1 0 1	0	1	0 1 0 1
0	0	1 0 0 1	0	1	0 1 1 0
0	0	1 0 1 0	0	1	1 0 1 0

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Determining the Circuit Delays

The propagation delays in the circuit can be determined by measuring the time delay between a clock edge and given output

By default the waveforms are display in picosecond time units. It is more convenient to redefine these as nanosconds
Select Options - Define Preferences from the DAI Signalscan Waveform window to display the Define Preferences menu
Select the option box Time Units at the top of the menu, click on the ns Time Units (10^-9 ) button and select OK

To achieve an accurate measurement it is necessary to zoom into the required area of the display
Select ZoomInX from the DAI Signalscan Waveform window repeatedly until you begin to see a definable delay between a positive going clock edge and an output transition. You may need to use the scroll bar at the bottom of the display to bring the required areas of the waveforms into view.

Use the left mouse button to click on a positive going clock edge. Cursor 1 will be locked onto this transition
Use the middle mouse button to click on a resulting output transition. Cursor 2 will be locked onto this transition
The time display at the top left of the window shows the difference between the two cursors i.e. the time delay between the two  transitions

The display below shows a delay of 3.863 ns between a clock edge and a high to low transition on output a

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Leaving CADENCE

Exit from the DAI Signalscan Waveform window by selecting File - Exit
Confirm the action by clicking on Exit when requested

Close down the Verilog-XL Integration Control menu by selecting File - Quit
Confirm the action by clicking on Yes when requested

Select Window - Close on the schematic window to close the window.

Select File - Exit on the CIW to exit CADENCE.

The message "OK to exit icfb?" will be displayed. Select Yes to complete the exit operation.

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