Digital Integrated Circuit Design
Standard Cell Design Walkthrough 2
Entry, Simulation and Synthesis of VHDL Components
Contents
- Walkthrough Overview
- Conventions Used in this Walkthrough
- Setting the Design Directory
- VHDL ENTRY AND BEHAVIORAL SIMULATION
- VHDL SYNTHESIS
Walkthrough Overview
This walkthrough details the design flow for the VHDL specification, behavioral simulation, synthesis and gate level simulation of a BCD counter circuit.
The design flow uses the CADENCE tools Leapfrog for VHDL behavioral simulation, Ambit for synthesis and Verilog for gate level simulation. The MIETEC design kit provides standard cell components for synthesis, symbols for schematic display and functional models for the gate level simulation.
Conventions Used In This Walkthrough
1) All commands typed at operating system
prompts should be terminated with the RETURN key.
Unix commands must be
entered in lower case unless otherwise stated.
2) Operations involving the mouse will use the left hand mouse button unless otherwise stated.
3) Options selected from sub menus will be indicated as :-
Main Menu option - Sub menu Option - Sub Menu Option
E.g. File - New - Library
Setting the Design Directory
Before beginning the design walkthrough it is necessary to create a separate subdirectory vhdl within the stdcell design directory for your vhdl work and to copy the VHDL source file bcdcount.vhd and testbench file testbcdcount.vhd for the bcd counter into this subdirectory.
Type the following commands against the UNIX prompt terminating each with the RETURN key :-
cd stdcell [Move into the design directory stdcell]
mkdir vhdl [Create the vhdl subdirectory]
cd vhdl [Move into the vhdl subdirectory]
cp /staff/examples/mietec/bcdcount.vhd bcdcount.vhd [Copy file bcdcount.vhd]
cp /staff/examples/mietec/testbcdcount.vhd testbcdcount.vhd [Copy file testbcdcount.vhd]
VHDL ENTRYAND BEHAVIORAL SIMULATION
This section details the operating procedure for using Leapfrog to enter and simulate the BCD counter.
Instructions are provided for creating, compiling, elaborating and simulating the VHDL code.
Starting Leapfrog
Start the Leapfrog Simulator by typing the following command at the UNIX prompt and terminated by the RETURN key :-
cadence -vhdl
The Notebook Startup menu will appear displaying
options for initialising Leapfrog.
Create a work area in your vhdl directory by clicking
on the Continue in this directory button.
OK the form
The Cadence Leapfrog - Simulation window will appear. The window provides a tool bar for the top level menu commands and two display windows for file information. The left window displays the library browser (compiled files in the work directory) whilst the right window displays the file browser (source files).
Check also that the copied files bcdcount.vhd and testbcdcount.vhd are listed in the file browser.
The display should now be as shown below
Creating a Work Library
Prior to simulation all VHDL design entities must be compiled
into a library named work
This library is implemented as a subdirectory located in the
directory containing your VHDL source files.
The following instructions explain how to create the work
library
Note: This only needs to be carried out once
for each new project.
Select Edit -> Libraries... from the Cadence Leapfrog
- Simulation window
The Library Path Editor form is displayed
Select Edit -> Add library... to display the Add Library form
Enter work into the Name box as shown below
Click on OK to create the library
Check that a new entry has appeared in the Library Path Editor form referencing the work directory as shown below
The Path will be set to your own design directory on the system
Select File - Save to save the new library entry
Select File - Exit to close the Library Path Editor
Return to the Cadence Leapfrog - Simulation window, click on the downwards scroll arrow to the right of the Library box and select work for the work library.The display should now be as shown below.
Creating / Editing the Circuit and Testbench Files
The Leapfrog editor can be used to create and edit the circuit
and testbench files
If the file does not exist it will be created. If it already
exists it will be opened
Select File - Open - File from the Cadence Leapfrog -
Simulation window to display the Open File form.
Enter the file name bcdcount.vhd into the File box and select OK
The copied VHDL circuit file for the bcd counter is displayed as shown below
Select File - Close from the editor window to close the file
Repeat the above process for the copied testbench file testbcdcount.vhd for the counter as shown below
Select File - Close from the editor window to close the file
Compiling and Elaborating the Design
The design is prepared for simulation in three stages :-
1) The circuit file is compiled
2) The testbench file is compiled
3) The testbench file is elaborated. This
combines the circuit and test information for input to the
simulator
Click on the file bcdcount.vhd in the File Browser.
Ensure that it highlights
Select Tools - Compile to display the Compile VHDL Design
form.
Click on the Work Library button to select work as the work
library
Select OK to initiate the compile process
Check that there are no errors reported in the status window at the bottom of the Cadence Leapfrog - Simulation form and that the compiled file bcdcount has appeared in the Library Browser.
Repeat this process for the test bench file testbcdcount.vhd
The Work Library button will still be active for this and
any other subsequent compiles so simply OK the Compile
VHDL Design form
Check that the compiled file test_bcdcount appears in the
Library Browser
At this point you can double click on each of the compiled
files to reveal their underlying design units
bcdcount will have a VHDL Entity named entity and a VHDL Architecture
named behaviour
test_bcdcount will have VHDL Entity named entity and VHDL
Architecture named test
The display at this point should be as shown below
Click on the VHDL Architecture test in the Library Browser
and ensure that it highlights with a surrounding box.
Select Tools - Elaborate to display the Elaborate VHDL
Design form
The form indicates that a simulation snapshot file sim will
be created for simulation.
Click on OK to initiate the elaborate process and check that VHDL Simsnapshot sim has been added to the design unit test as shown below.
Simulating the Design
Click on the VHDL Simsnapshot sim and ensure that it highlights
with a surrounding box
Select Tools - Simulate to display the Run VHDL Simulation
form and OK the form
After a short delay the Leapfrog VHDL Simulator
Menu will appear
The top window displays the VHDL code for the design unit
to be simulated
The bottom window displays status information and accepts
simulation control commands
The middle window displays the current simulation time and
a list of design units in the design
Double clicking on a design unit will display its code in
the top window
Ensure that WORK.TEST_BCDCOUNT:TEST is selected before proceeding
Signals to be displayed in the simulation can be selected
by clicking on their names in the VHDL code
Hold down the Ctrl key so that more than one signal can be
selected and click in turn on signals CLK, RESET, UNIT and
TEN. Check that they highlight and that the display is now
as shown below.
Select Wave Trace from the menu to open up the DAI Signalscan
Waveform window as shown below
The waveforms at the moment will be set as undefined (U) and
coloured purple
Click back in the Leapfrog VHDL Simulator window and run the simulation for 1200 ns with the following command typed against the > prompt in the bottom window :-
run 1200 ns
In order to see the complete simulation it will be necessary to select ZmOutXFull from the top toolbar of the waveform window
The display should now be as shown below
Inspect the waveforms to verify that the circuit is functioning correctly.
Click back in the Leapfrog VHDL Simulator window.
Select Restore to re-initialise the simulator.
Re-run the simulation with a time of 12000 ns to test the complete range of the counter
Check that the circuit successfully counts to 99 and cycles back to 0
Leaving Leapfrog
Exit from the waveform viewer by selecting File - Exit from
the DAI Signalscan Waveform window
Confirm the action by clicking on Exit when requested
Select Window - Quit in the Leapfrog VHDL Simulator window to close the window
Select File - Exit Notebook in the CADENCE Leapfrog -
Simulation window to exit from Leapfrog
In response to the message "Do you really want to exit the
project Notebook?" click on Yes.
VHDL SYNTHESIS
This section details the operating procedure for using Ambit to synthesise the VHDL code for the bcd counter.
Instructions are provided for compilation, synthesis and optimisation into MIETEC library components and the subsequent generation & display of the circuit schematic
Starting Ambit
Start the Ambit Synthesiser by typing the following command at the UNIX prompt and terminated by the RETURN key :-
cadence -synth
After a short delay the NaviGates menu will be displayed as shown below
Selecting the Target Technology
Before synthesising the design it is necessary to define the Mietec process as the target technology to be used in the construction of the bcd counter schematic.
Select File - Read Library (or the Tech icon) from the NaviGates menu to display the Read ALF File menu
Select the file cmos24Cells.alf from the files list and ensure that the entry highlights as shown
OK the form and check that the Info: display at the bottom
of the Navigates menu shows the target technology
successfully set.
(Note: you may get some warnings relating to functions not
defined for certain cells. These can be ignored)
Reading the VHDL Source File
Now read in the file to be synthesised by selecting File
- Read HDL (or the HDL icon)
The Read HDL Files menu will appear
Ensure that your vhdl directory is selected in the Directories
list
Click on the VHDL button to display the vhdl files in this
directory
Double click on the file bcdcount.vhd in the Available
Files list
Ensure that the filename highlights and its pathname is entered
into the Selected Files list
OK the form and check that the Info: display at the bottom of the Navigates menu shows a successful read
Synthesising the Design
The synthesis process is implemented in two stages. A circuit schematic is first created using generic components and then optimised into the target technology (Mietec) components
To construct the generic schematic select Tools - Build Generic (or the Build Generic icon at the centre of the toolbar)
Upon completion the synthesised design modules will be displayed
in the Modules list
The generic schematic for the top level of the design can
be displayed by double clicking on the BCDCOUNT entry as shown
below.
Likewise the schematics for any of the lower level modules can be viewed by double clicking on their respective entries.
To optimise the design select Tools - Optimize (or the Optimize
icon adjacent to the Build Generic icon)
The Optimize Options form will appear. This enables
the design to be optimized either for speed (time) or silicon
(area). For this exercise leave the settings as default (time)
and click on the Optimize button.
Upon completion the optimised flattened schematic is displayed
together with its associated area data.
Note: You may get an error message relating
to a cmos24Cellstech file. This can be ignored.
You can inspect any part of the final schematic simply by
holding down the left hand mouse button and dragging the cursor
to define an area you wish to zoom into.
Selecting View - All will return to the complete schematic.
Save the synthesised database by selecting File - Write ADB...
Enter bcdcount.adb in the Files: box
Ensure that the Netlist Format button is
set to ADB
OK the form and check that the Info: display at the bottom
of the Navigates menu shows a successful write
(Should you wish to recall the synthesised schematics in Ambit at some later date the saved database can be recalled as follows :-
Read in the cmos24Cell.alf technology file as previously
described
Select File - Read ADB... and enter the database filename
bcdount.adb in the Files: box.
OK the form)
Creating a Verilog Netlist
The synthesised circuit is imported into the stepper motor design by creating a Verilog netlist.
Select File - Write HDL... to display the Writing Module form
The Verilog netlist will need to be written to the smotor
directory that contains the other design schematics
Ensure that the directory smotor is selected in the Directories
list (you may need to double click on stdcell)
Enter bcdcount.v for the filename in the Files:
box
Ensure that the Verilog button is set.
The form should now be as shown below
OK the form and check that the Info: display at the bottom of the Navigates menu shows a successful write
Exit from Ambit by selecting File - Exit and confirm when requested
GATE LEVEL SIMULATION
This section details the operating procedure for reading the synthesised schematic into the smotor design database and performing a gate level simulation to verify that a correct synthesis has taken place.
Instructions are provided to import the Verilog netlist, create a testfixture file, run the Verilog simulator and display graphically the output results.
Importing the Verilog Netlist
The Verilog netlist for the bcd counter schematic will be read into the smotor design
Click back into the UNIX window
Move back into the smotor directory
cd ../smotor [move up one level and down into smotor]
To simplify the setting up of the Verilog import process
a parameter file vin.par has been provided
Copy this into your smotor directory
cp /staff/examples/mietec/vin.par vin.par
Start the CADENCE design system with the MIETEC design kit
cadence -mietec
Select File - Import - Verilog from the CIW menu to display
the VerilogIn form
Select Load from the VerilogIn form to display the
Load Parameters form
Enter vin.par into the Load From: box and select
OK
Observe that additional data for the Reference Libraries
and -v options is now added to the VerilogIn
form
Now define the target library in which to import the Verilog
schematic and the file to import
Click in the Target Library Name box and enter smotor
Click in the Verilog Files to Import box and enter
bcdcount.v
Check that the VerilogIn form is now as shown below
OK the form.
Upon completion of the import process a VerilogIn status
window will open
Click OK to view the log file. Check that both the BCDCOUNT
symbol and schematic have been checked in.
Select File - Close Window to close the log file
Simulating the Synthesised Schematic
The Verilog gate level simulator will be used to simulate the synthesised bcd counter schematic
Select File - Open from the CIW to display the Open File form
Select :-
smotor as the Library Name
BCDCOUNT as the Cell Name
schematic as the View Name
OK the form to display the BCDCOUNT schematic which should be as shown below
Select Tools - Simulation - Verilog-XL from the schematic
window
OK the Setup Environment form
The Verilog-XL Integration Control menu appears
(Note: You may have to use the Alt/F7 keys to re-position
the menu on the screen)
Select Stimulus - Verilog from the Verilog-XL Integration
Control menu
Select Yes to create a testfixture when requested
Refer to the "Gate Level Simulation" section in Walkthrough 1 if necessary for information on how to perform the following :-
Use the Copy command to copy the default stimulus file testfixture.verilog to a new file testfixture.new. Remember to activate the Make Current Test Fixture button.
Edit the testfixture.new file adding suitable test vectors
to properly test the circuit.
Note: The input signals CLK and RESET will
be defined in upper case in the file. You must therefore use
this convention when refering to these signals throughout
the rest of the file.
Save the file
Remove the +dlverbose option from the Simulation Options
menu
Run the simulation
Expect to get warnings relating to potential spikes and glitches
in the circuit
Display the simulation results and check that the circuit operates the same as that observed by the VHDL functional simulation
Leaving CADENCE
Select File - Exit in the Signalscan Waveform window and confirm when requested
Select File - Quit in the Verilog-XL Integration Control window to exit Verilog and confirm when requested
Select Window - Close in the Schematic window to close the window.
Select File - Exit on the CIW to exit CADENCE.
The message "OK to exit icfb?" will be displayed. Select Yes to complete the exit operation.