Digital Integrated Circuit Design
Standard Cell Design Walkthrough 3
Entry and Simulation of Full Custom Components
Contents
- Walkthrough Overview
- Conventions Used in this Walkthrough
- Setting the Design Directory
- SCHEMATIC ENTRY
- SIMULATION
- LAYOUT SYNTHESIS
- ABSTRACT GENERATION
- FUNCTIONAL MODEL
Walkthrough Overview
This walkthrough details the design flow for the schematic entry, simulation and physical realisation of a stepper motor direction display circuit using a full custom component constructed from MIETEC 2 micron standard cell library transistors.
The design flow uses the CADENCE tools Composer for schematic entry, Spectre for circuit simulation and the layout synthesiser LAS for mask level cell generation.The MIETEC design kit provides the transistor symbols for schematic entry, the models for simulation and the physical layout for synthesis
Conventions Used In This Walkthrough
1) All commands typed at operating system
prompts should be terminated with the RETURN key.
Unix commands must be
entered in lower case unless otherwise stated.
2) Operations involving the mouse will use the left hand mouse button unless otherwise stated.
3) Options selected from sub menus will be indicated as :-
Main Menu option - Sub menu Option - Sub Menu Option
E.g. File - New - Library
Setting the Design Directory
Before beginning the design walkthrough it is necessary to move into the design sub-directory previously created.
Type the following command against the UNIX prompt terminating with the RETURN key :-
cd stdcell/smotor [Move into sub-directory smotor ]
SCHEMATIC ENTRY
Introduction
This section details the operating instructions for invoking CADENCE and running Composer to enter the stepper motor direction display schematic.
Instructions are provided for entering transistor components, input/output pins and wires and for checking and saving the design.
A modified version of the circuit will also be created for simulation purposes.
Starting CADENCE
Start the CADENCE design system with the MIETEC design kit by typing the following command at the UNIX prompt and terminated by the RETURN key :-
cadence -mietec
After a short delay the CADENCE Command Interpreter Window (CIW) as shown below will appear. The window provides a tool bar for the top level menu commands and a display window for status information.
Creating a New Cellview
Select File - New - Cellview from the CIW to create
a new cell, display, for the direction display circuit
The Create New File form shown below will be displayed
Click in the Library Name box and scroll down the list of libraries to select smotor
Click in the Cell Name box and enter the cell name display
Click in the Tool box and scroll down the list of tools to select Composer-Schematic
Check that the View Name has automatically been entered as Schematic and that the form now appears as shown above.
Accept the form by clicking on OK.
The Composer-Schematic Editing window will now appear. This can be enlarged to full size if required by clicking on the square icon at the top right of the window.
The Display Schematic
The schematic window displays the main options along the top and a subset of these options in icon form down the left hand side.
The circuit schematic shown below will be constructed
Entering the Schematic
Select Add - Instance ( or use the i key on the keyboard) to display the MIETEC Design Kit Library menu as shown below.
Click in the scroll box immediately to the right of the Library Name box and select mie24Lib from the list of libraries.
Additional menus will now be added to the form. You may need to enlarge this form vertically and horizontally by pressing and holding down the left hand mouse button on the bottom right hand corner of the window whilst dragging the mouse to the new required position.
Click in the Devices Box underneath the Full Custom Device Library heading to display the categories of full custom components available.The form should now be as shown below
Click in the Active Devices box to display the list of available transistors and select pmos from the list.
Place two instances of the pmos transistor.
Repeat the above process to place two instances of the nmos transistor
Select pwrvdd from the Supply box for the pwrvdd power supply symbol and place
Select gndvss from the Supply box for the gndvss ground symbol and place
Add pins for the dir input and the sega and segcd outputs
(segcd is the output of the first inverter, sega is the output of the second inverter)
Wire up the components and the input/output pins
Check and Save the design
Creating the Test Schematic
In order to simulate the display circuit it is necessary to construct a test circuit, testdisplay, that contains the display circuit plus additional external components that provide the power supply and input signal.
The test circuit will be created by making a copy of the original display circuit
Select Tools - Library Manager from the CIW to display the Library Manager form
Click on smotor in the Library column, display in the Cell
column and schematic in the View column
The form should now be as shown below
Select Edit - Copy from the form to display the Copy View form
Locate the To section of the form
Enter smotor for the Library, testdisplay for the Cell and
schematic for the View
The form should now be as shown below
Select OK to initiate the copy
Observe that the new cell has been added to the cell list
of the Library Manager form
Close the Library Manager form by selecting File
- Exit
Open the new testcircuit schematic by selecting File - Open from the CIW and entering testdisplay for the Cell Name on the Open File form.
The circuit will be modified to that shown below
A ground short (gnd_gndvss), a dc voltage source (vdc) and
a pulse voltage source (vpulse) will be added
The ground short ensures that the gndvss supply pin is connected
to a true ground (gnd) for simulation
Select Add - Instance (or use the i key) to display the Mietec 2um CMOS Design Kit Library Menu
To add the ground short, ensure that the mie24Lib library
is still selected
Click on the Ground Shorts box, select the gnd_gndvss component
and place
Select Add - Instance (or use the i key)
From the Mietec 2um CMOS Design Kit Library Menu click in the scroll down box to the right of the Library Name box and select analogLib as shown below
To add the dc voltage source click in the scroll down box to the right of the Cell Name box to display the available analogue components
Select vdc from the list. The menu expands to allow the component
parameters to be added
Enter 5 V for the DC voltage as shown below
Place the component
Repeat for the vpulse symbol entering the following values
and place.
You may need to enlarge the menu vertically
Voltage 1 0.0 V
(initial pulse voltage)
Voltage 2
5 V
(final pulse voltage)
Delay Time 10n s
(delay before start of pulse)
Rise Time 1n s
(pulse rise time)
Fall Time 1n s
(pulse fall time)
Pulse Width 50 n s
(pulse width)
Wire up the new components
Check and Save the design and leave the schematic window open
SIMULATION
Introduction
This section details the operating instructions for performing a circuit simulation using Spectre
Instructions are provided for netlist generation, specification of transient analysis parameters, simulation and display of output results for the circuit.
Running Spectre
Select Tools - Analog Artist from the schematic window to display the Analog Artist Simulation form.
Select Analyses - Choose (or the AC TRAN DC icon second down from the top) to display the Choosing Analysis Simulation form.
Verify that the tran button is selected. Click in the Stop Time box and enter 100n. This defines a transient analysis from 0 to 100 nano seconds
The form should be as shown below
Select OKand check that the parameter has been entered into the Analyses section of the Analog Artist Simulation form as shown below
Select Simulation - Run (or the traffic light icon)
Observe the CIW for status information relating to the production and compilation of the circuit netlist and the running of the simulation. Any errors produced must be corrected and are likely to relate to incorrectly specified components, connections or properties associated with the power supply and input signal sources on the schematic.
Displaying Results
Select Results - Direct Plot - Transient Signal from the
Analog Artist Simulation form
After a short while a blank waveform window will open and
the schematic window will be displayed
Signals are displayed in the waveform window by selecting their wires in the schematic
Click on the input wire, the segcd wire and the sega wire in the schematic and verify that they highlight in different colours
Press the Esc key to display the selected signals in the waveform window as shown below
Select Axes - To Strip from the waveform window to display the signals individually as below
Verify that the circuit is functioning correctly
Select Window - Close to close the waveform window
Select Window - Close to close the schematic window
Select Session - Quit to close the Analog Artist Simulation
form
In response to the message "Do you wish to save the current
state?" select Yes if you wish to save the transient analaysis
parameters and the waveforms or No if you don't.
LAYOUT SYNTHESIS
Introduction
This section details the operating instructions for running the layout synthesiser LAS.
Instructions are provided for generating compacted and geometric layouts for the display circuit
Running LAS
Before running the synthesiser it is necessary to load the original display circuit
Select File - Open from the CIW to display the Open file
form
Select smotor as the Library Name, display as the Cell Name
and schematic as the View Name.
OK the form to load the original display circuit
Select Tools - Design Synthesis - Layout Synthesis
Observe that the schematic window menu now displays an LAS
option.
Before proceeding it is necessary to constrain the synthesiser to allocate a metal 2 terminal for the cell input pin dir instead of the default polysilicon. The output terminals secd and sega will be allocated metal 2 by default. This will enable the cell to be connected by the metal 2 interconnect used during the automatic place and route of the complete design.
Select LAS - Generate Cell to display the Generate Options form
Select Pin from the Generate form to display the Pin Constraints form
Verify that the pin name dir is entered in the Terminal Name(s) box
Click the any button in the Pin Constraints section and select M2 from the Layer box underneath. This will position the dir pin on any side of the display cell and configure for metal 2 interconnect. The form should now be as shown below.
Select Merge to register the constraint and OK the form
Select OK on the Generate form to initiate the synthesis.
During the synthesis the Layout Selection Window (LSW) will appear. This will not be used in the process so can be iconised. It will close when the exit from CADENCE takes place at the end of the session
Upon completion the syntheser will open a Virtuoso Editing window with the cell layout displayed as a compacted view.
The full layer set (including the contact points) can be
displayed by selecting Options - Display to show the Display
Options form. Locate the Display Levels section towards
the bottom of the form and enter 100 in the To section.
OK the form
Check that the cell layout is now as shown below with all input and output pins allocated metal 2 (light blue)
The final stage in sythesis is to generate a correct geometrical structure with all contact points allocated.
Select Tools - Compactor from the Virtuoso Editing window and observe that the Compact option now appears on the menu.
Select Compact - Convert To Geometric to display the Convert to Geometric form
OK the form to initiate the geometric conversion
The final cell construction should now be as shown below as a layout view
Select Design - Save for the compacted view
Select Design - Save for the layout view
Close the compacted view by selecting Window - Close
Close the schematic window by selecting Window - Close
Leave the layout window open
ABSTRACT GENERATION
Introduction
An abstract view is required for the cell so that it can be placed with the other standard library cells during the automatic place and route process.
Running the Abstract Generator
Select Tools - Abstract from the layout window to display
the Select PR Engines form
Ensure that the CE/BE button is activated and OK the form
This selects the Cell Ensemble/Block Ensemble editor for the
Place & Route Engine
Select Abstract - Set Cell Props to display the Set Cellview
Properties form
Click in the scroll box for Cell Type and select standard
as shown below
OK the form. This ensures that the cell can be placed on a cell row with the other standard cells rather than as a macro requiring a specific placement.
Select Abstract - Abgen to display the Create Abstract form
Click in the Rules Library box and enter mie24TechLib (note the use of capital letters for T and L) as shown below.
OK the form to generate the abstract. Check the CIW for any errors.
The abstract can now be viewed
Select Design - Open to display the Open File form
Select smotor for the Library Name, display for the Cell Name
and abstract for the View Name and OK the form
Check that the abstract is as shown below
Select Design - Save in the abstract window
FUNCTIONAL MODEL
Unlike the standard cells in the design the display circuit
has no behavioral Verilog model. This must be
created and verified before the complete top level circuit
can be simulated
Creating the Functional Model
Select Design - Open from the abstract window and load the display schematic
From the display schematic window select Design - Create
Cellview - From cellview
The Display Cellview from Cellview form appears
Scroll down the Tool / Data Type box and select Verilog Editor
Check that the To View Name box is now set to functional as
shown below
OK the form
An edit window opens with a Verilog template for the display circuit as shown below
Modify the template to include two additional functional statements as shown below
assign sega = dir sets
output sega equal to the value of dir
assign segcd = !dir sets output segcd
equal to the inverse of the value of dir
Select File - Save (needed) to save the file
Select File - Close to close the editor window
The file is checked for errors. Correct if errors occur.
Leaving CADENCE
Select Window - Close in the schematic window to close the window
Select File - Exit on the CIW to exit CADENCE.
The message "OK to exit icfb?" will be displayed. Select Yes to complete the exit operation.
Creating a Test Pattern File for the Functional Model
Before incorporating this model into the top level chip simulation it is necessary to verify its correct operation. This will be done with the Verilog-XL stand alone simulator and a suitable test pattern file.
Click on the Text Editor icon ( notepad and pencil) on the
UNIX desktop toolbar.
Enter in the following text as the test pattern file.
The following is an explanation of the file contents
| Statement | Description |
|---|---|
| module display_test ; | Declares a module called display_test |
| reg dir; | Specifies the input signal(s) dir |
| wire sega,segcd; | Specifies the output signals sega and segcd |
| dir = 1'b0; #100 dir = 1'b1; #100 dir = 1'b0; |
Defines dir as a 1 bit signal and sets to logic 0 Sets dir to logic 1 100 ns later Sets dir to logic 0 100 ns later |
| #100 $stop; | Stops the simulation 100 ns |
| display dut(sega, segcd, dir); | Defines the module display as the device under test (dut) and defines its input and output signals |
Select File - Save As from the Text Editor toolbar
Move down the directory structure in the folders list as follows
:-
smotor > display > functional
Save the file with the file name verilogtest.v
(This directory is chosen to be the same as where the system saved the circuit file verilog.v)
Simulating the Functional Model
Move into the directory that contains the verilog circuit and test pattern files for the display model by typing at the UNIX prompt :-
cd smotor/display/functional
Invoke the Verilog stand alone simulator by typing :-
cadence -verilog verilog.v verilogtest.v [also compiles the circuit file verilog.v and test file verilogtest.v]
The Cadence Verilog-XL menu will open as shown below with the code for the module display_test displayed.
[Note: Should there be errors in the test
pattern file you will need to go back to the Text Editor and
correct.
You can re-compile the corrected file by selecting File -
Reinvoke from the Cadence Verilog-XL menu]
Select Control - Reset Simulation to reset the simulator to time zero
Select the signals to be displayed by the simulator by holding down the Ctrl key and clicking on dir, sega and segcd in turn anywhere they appear in the dipslayed code listing. Ensure that all selected signals highlight.
Select Tools - Waveform to display the Signalscan Waveform viewer
Select Control - Run (or the triangular Run icon) to run the simulator
Click back in the Signalscan Waveform viewer and observe the waveforms which should be as shown below
Check for correct functionality
If you wish to repeat the simulation select Control - Reset Simulation before re-running
Close the Signalscan Waveform viewer by selecting File - Exit and confirm when requested
Close the Cadence Verilog-XL menu by selecting File - Exit