Digital Integrated Circuit Design
Standard Cell Design Walkthrough 4
Final Assembley, Simulation and Layout
Contents
- Walkthrough Overview
- Conventions Used in this Walkthrough
- Setting the Design Directory
- SCHEMATIC ENTRY
- SIMULATION
- LAYOUT
- Introduction
- Generating an Autolayout
- Initialising the Placement
- Positioning of the Peripheral Cells
- Placement of the Peripheral Cells
- Placement of the Corner Cells
- Peripheral Cell Alignment
- Placement of Logic Cells
- Generation of the Routing Channels
- Specification of Mietec Power Supply Requirements
- Global Routing
- Detailed Routing
- FINAL DESIGN CHECKS
Walkthrough Overview
This walkthrough details the design flow for the creation, simulation and layout of the final stepper motor controller circuit. The driver, bcdcounter and display circuits will be assembled on to a top level schematic with appropriate peripheral signal and power pads.
The design flow uses the CADENCE tools Composer for schematic entry, Verilog for gate level simulation and Cell Ensemble for placement and routing.
Conventions Used In This Walkthrough
1) All commands typed at operating system
prompts should be terminated with the RETURN key.
Unix commands must be
entered in lower case unless otherwise stated.
2) Operations involving the mouse will use the left hand mouse button unless otherwise stated.
3) Options selected from sub menus will be indicated as :-
Main Menu option - Sub menu Option - Sub Menu Option
E.g. File - New - Library
Setting the Design Directory
Before beginning the design walkthrough it is necessary to move into the design sub-directory previously created.
Type the following command against the UNIX prompt terminating with the RETURN key :-
cd stdcell/smotor [Move into sub-directory smotor ]
SCHEMATIC ENTRY
Introduction
This section details the operating instructions for invoking CADENCE and running Composer to assemble the stepper motor contoller schematic.
Instructions are provided for generating and connecting symbols for the driver, bcdcount and display circuits and the addition of peripheral signal and power pads.
Starting CADENCE
Start the CADENCE design system with the MIETEC design kit by typing the following command at the UNIX prompt and terminated by the RETURN key :-
cadence -mietec
The CIW opens
Creating Symbols
Select File - Open from the CIW
Enter smotor for the Library Name, driver for the Cell Name
and schematic for the View Name
The driver schematic is displayed
Select Design - Create Cellview - From Cellview from the schematic window menu
The Cellview for Cell view form appears. OK the form to display the Symbol Generation Options form as shown below.
The form details the pin designations on the left and right
sides of the symbol.
Select OK to accept these designations.
The symbol is now generated and displayed as shown below
Select Window - Close to close the symbol window
Select Window - Close to close the schematic window
Repeat this process for the bcdcount and display schematics to generate their respective symbols as below
Creating the Top Level Schematic
Select File - New - Cellview from the CIW to create a new cell, chip, for the top level circuit
The Create New File form will be displayed
Click in the Library Name box and scroll down the list of libraries to select smotor
Click in the Cell Name box and enter the cell name chip
Click in the Tool box and scroll down the list of tools to select Composer - Schematic
Check that the View Name has automatically been entered as schematic
Accept the form by clicking on OK.
The Composer-Schematic Editing window will now appear. This can be enlarged to full size if required by clicking on the square icon at the top right of the window.
The circuit schematic shown below will be constructed
Entering the Symbols
Select Add - Instance ( or use the i key on the keyboard) to display the MIETEC Design Kit Library Menu
Click in the scroll box immediately to the right of the Library Name box and select smotor from the list of libraries. The menu should now be as shown below
Click in the scroll down box to the right of the Cell Name
box to display the available library symbols.
Select driver from this list and ensure that the View is set
to symbol as shown below
The driver symbol is attached to the cursor. Place in a suitable position on the schematic
Repeat this process for the bcdcount and display symbols placing as shown below
Entering the Peripheral Signal and Power Pads
Before placing the peripheral pads you may wish to zoom out
the schematic display
Select Window - Zoom Out By 2 (or the [ key )
Select Add - Instance and from the MIETEC Design Kit Library Menu click in the Library Name scroll down box to select the mie24Lib library.
Click in the Digital box to display the types of Digital
Standard Cells available.
Click in the Digital IO Pads scroll down box and select IT.
This specifies a TTL compatible input pad
Place three instances of this pad for the clk, dir and reset
inputs
Allow sufficient spacing between pads
Before placing the output pads you may wish to zoom out again
Repeat the above procedure to select the O2 output pad and
place 14 instances
Place the power supply pads by selecting digital_supply from the Dig Pwr Supply scroll down box
In order to perform a top level simulation on this schematic it is necessary to connect input pins on the input of the IT pads and output pins on the output of the O2 pads.
Place and name the input and output pins as follows :-
inputs clk reset dir
outputs a b c d ten3 ten2 ten1 ten0
unit3 unit2 unit1 unit0 sega segcd
Wire up the components
Note: The outputs of the bcdcount symbol are busses and must be named as such
Select Add - Wire Name ( or the l key) to display the Add
Wire Name form
Enter ten<3:0> in the Names box as shown below and press
RETURN
The name is now attached to the cursor
Position the name adjacent to the wire to be named and click
the mouse button
The name will now be fixed in position
Now point at the wire that the label names and click again
to attach the name to the wire
Repeat for the unit<3:0> bus
Each individual wire from a bus must be named in a similar
fashion
For example the wires for the unit<3:0> bus are named unit<3>unit<2>unit<1>
and unit<0> as shown below
Check and Save the design and correct any errors that may
be reported in the CIW
Leave the schematic window open
SIMULATION
Introduction
This section details the operating instructions for performing a gate level simulation on the stepper motor controller circuit.
The procedure is the same as that for the simulation of the individual circuits. General instructions are given below, refer if necessary to the previous walkthroughs for the specific details.
Running Verilog
Select Tools - Simulation - Verilog - XL from the schematic
window
OK the Setup Environment form
Remember to remove the +dlverbose option from the Other Options box on the Simulation Options form
(Select Setup - Simulation on the Verilog - XL Integration Control menu, select More on the Simulation Options form and extend the form vertically to display the other Options box)
Select Stimulus - Verilog from the Verilog -XL Integration Control menu and respond Yes to the creation of the testfixture.verilog stimulus template file.
Copy the testfixture.verilog file to the file testfixture.new
View the testfixture.new file and check that it is as shown
below
Edit the testfixture.new file to include the test vectors as shown below
Save the file and close the editor
Start and Continue the simulation checking the CIW for possible errors
Expect to get warning information as the simulation proceeds relating to timing hazards through individual components in the design. The simulator is identifying signals that may have spikes and glitches.
View the waveforms and check that the circuit is operating correctly as shown below
Measure the propagation delay between a clock edge and an output signal of your choice (as detailed in Walkthrough 1). Note this value down. It will be used for comparison in the post layout simulation.
Close the DAI Signalscan Design Browser and Waveform windows
Viewing Internal Signals
When diagnosing design errors it is often useful to display signals on wires internal to a circuit. The easiest way to do this is to capture all signals in the design by changing an option on the Verilog Record Signals form. To demonstrate this we shall display one of the signals in the driver module.
Click back in the Verilog - XL Integration Control menu
Select Setup - Record Signals to display the Record Signals
Options form
Locate and click in the scroll box displaying "Top Level Primary
I/O" and select All Signals
OK the form
Re-run the simulation
Observe that this time the DAI Signalscan Design Browser now lists all signals at the top level in the "Nodes/Variables in Current Context" section and the instance numbers of the three top level modules in the "Instances in Current Context" section.
Now click back to the schematic and note the instance number
of the driver module (located in yellow at the top right of
the symbol).
Select Design - Hierarchy - Descend Edit, click on the driver
symbol and OK the Descend form
The bcdcount schematic is now displayed
Click on any of the internal wires (one from an EXOR gate
output is suitable) and ensure it highlights
Select Edit - Properties - Objects (or the Property icon)
to display the Edit Object Properties form.
Note the Net Name in the Edit Object Properties form.
Cancel the form
Click back in the DAI Signalscan Design Browser and
select the instance name of the driver module.
The signals within that module will be listed
Select the net name of your chosen internal wire and observe
that it is added to the left hand signal list
Add this and any other selected signals to the waveform window
(AddtoWave) and display
Close the DAI Signalscan Waveform and Design
Browser windows
Close the Verilog - XL Integration Control menu
Click back in the schematic window and select Design - Hierarchy - Return To Top to re-display the chip schematic. Leave this window open, the instance numbers of the peripheral cells will be required during layout
LAYOUT
Introduction
This section details the operating instructions for running Cell Ensemble to place and route the cells of the stepper motor controller design
Instructions are provided for the manual placement of peripheral cells and the automatic placement and routing of the logic cells.
Generating an Autolayout
Before placement can begin an autoLayout cellview of the design must be created. This provides a graphical representation of the chip layout with abstract views of the peripheral and logic cells
Select File - Export - PR Flatten from the CIW to display
the Preview Flatten form.
Enter smotor for the Library Name, chip for the Cell Name
and schematic for the View Name
Check that the form is now as shown below
OK the form and check the CIW for a successful autoLayout generation
Select File - Open from the CIW to display the Open File
form
Ensure the Library Name is set to smotor and the Cell Name
to chip.
Scroll down the View Name box and select autoLayout
OK the form. The autoLayout will now be displayed as shown below.
The Layer Selection Window (LSW) will also appear. This will not be needed and can be iconised
The display details all the peripheral and logic cells in the design in no particular placement order
Select Tools - Floorplan/P&R - Cell Ensemble from the autoLayout window
This will configure the window for cell ensemble. The window display will remain the same but additional options will be added to the toolbar menu at the top of the window. The Object Selection Window (OSW) also appears. Leave this window open, it will be used in the placement process.
Initialising the Placement
Before placing the cells it is necessary to obtain an overall estimate of the chip area and to define two placement regions, one for the peripheral cells and the other for the logic cells.
Select Floorplan - Reinitialize from the autoLayout window
to display the Initialize Floorplan form
OK the form to accept the default settings and display the
initialized layout as shown below
This initialized layout now shows the esimated chip area with a default region in the middle for placement of the logic cells which are grouped together at the bottom right of the display. The peripheral dells will be arranged around this default region and are grouped together at the top of the display.
Positioning of the Peripheral Cells
To obtain an optimum layout and to accurately associate signals with the required pins on the package the placement of peripheral cells is always implemented manually.
The following guidelines should be observed when allocating peripheral cell locations :-
1) Distribute roughly equal numbers of cells on each side of the chip to obtain a square die
2) Centre power and ground cells on opposite sides to ensure efficient power distribution
3) Centre heavily used signal cells such as clock and resets so they can be routed equidistantly
3) Construct a floorplan for the main functional blocks in the design. Generally these blocks will be arranged so that signal flow between them demands minimum routing. Position the input/output cells in close proximity to their associated blocks. This assists the placer in producing the required floorplan.
The following peripheral cell placement would be suitable for the stepper motor controller design
The quickest way to define a peripheral cell placement is to construct a pad placement file.
Return to the UNIX window and copy the sample file pcells.plc into your design directory with the following command :-
cp /staff/examples/mietec/pcells.plc pcells.plc
Invoke the editor to view and modify this file by clicking
on the notepad and pencil icon on the UNIX desktop toolbar.
The Text Editor will open.
Select File - Open to display the Open a File form
Locate and double click on the stdcell directory in the Folders
list to display the smotor & vhdl directories
Double click on the smotor entry and scroll down the Files
list to locate the pcells.plc file.
Double click on this file to open in the Text Editor
The file (which can have any name and extension) will be as shown below
The sample file contains instance numbers for the peripheral cells that will not be the same as those in your design. These instance numbers will require modifying.
The format for signal cells is | I Instance number
| 0 Chip Side Position
Positions are numbered 0 to n as shown on the placement diagram
above
The format for power cells is | I Instance number
| Ix Chip Side Position
The power supply symbol on the schematic will have one instance
number but contains two cells
Hence IOVDD will be I0 and IOVSS will be I1
Modify the instance numbers in the file to match those on your schematic (displayed in yellow above the cell symbols).
Note: The instance number for the power supply cells can be obtained as follows :-
Click on the Digital Power Supply symbol and check that it
highlights
Select Edit - Properties - Objects from the schematic window
The Edit Properties form is displayed. Enlarge the
form if necessary.
The instance number is displayed in the Instance Name box
Select Cancel to quit from the form
Save the placement file (File - Save) and close the editor (File - Close)
Close the schematic window (Window - Close)
Placement of the Peripheral Cells
Before placing the peripheral cells it will be necessary to enlarge the chip boundary to accomodate all the cells in the positions required.
Click on the Design box in the OSW and ensure that it highlights along with the Instance box as shown below.
Click anywhere within the chip area in the autoLayout window and check that the chip boundary highlights in white.
Move the cursor to the top egde of the boundary and observe that the cursor changes to a horizontal bar with an upwards arrow.
Press and hold down the left mouse button and drag the boundary upwards until the dY value at the top of the autoLayout window reads approximately 800 (the value does not have to be exactly 800)
Release the mouse button and observe that the upper boundary has been stretched to a new position
Repeat the above procedure for the right boundary with a value of 800 for dX and check that the new boundary box is square
Select Design - Options - Display to display the Display
Options form
Locate the "Show Name Of" entry and click on the adjacent
Instance button.
This will display the instance numbers of the peripheral cells
to be placed
Select Place - IO Commands - Read Initial File to display
the Build IO Frame form.
Enter the file name pcells.plc in the IO Frame file box and
OK the form
The layout should now be as shown below but with your instance numbers displayed
Check that the cells are in the correct positions.
Note: An incorrect placement will most likely be due to a mistake in the placement file or an error in the enlargement of the chip boundary. Correct the file and/or reinitialize the layout and repeat the enlargement and placement procedure
Placement of the Corner Cells
Corner cells must now be inserted to allow continuous power supply routing around the peripheral cells.
Select Place - IO Command - Add Corners to display the
Insert IO Corner Cells form
OK the form and observe the addition of the four corner cells
as shown below
Peripheral Cell Alignment
All cells in the peripheral area must now be aligned in accordance with the design rules for the techology. This principally defines the minimum spacing between the cells.
Select Place - IO Command - Justify to display the Align
IO Frame form
OK the form. The display will not look noticably different.
To see the effect of this operation and to set up the display for routing it is necessary to set the display to a more detailed level.
Select Design - Options - Display again to display the Display
Options form
Locate the "Display Levels" entry. Leave the From box at 0
but click in the To box and set to 20
OK the form. The display will now resemble that shown below
Placement of the Logic Cells
Select Place - Automatic to display the Automatic Placement form
Locate the "Insert Feedthrough" entry and click on its adjacent
button
A feedthrough cell is an empty cell with tracking from top
to bottom enabling routing to pass through a logic cell row.
OK the form and check that the logic cells are placed as shown below
Generation of the Routing Channels
Before routing can take place it is necessary to define horizontal and vertical channels for the cell interconnect.
Select Route - Channels - Create to display the Create
Channels form
OK the form. The display will now show horizontal and vertical
boxes where the routing will be placed
Specification of Mietec Power Supply Requirements
The Mietec process defines a specific power supply distribution topology.This must be set before routing takes place.
Select Route - Modify Net - Update with mietec 2um parameters
and split supply/ground nets
The display will not change but status information will be
displayed in the CIW
Global Routing
The global router assigns nets to routing channels and then optimises this assignment but does not implement the actual routing
Select Route - Global Route - Automatic to display the Global Route Method form
Locate the "Options" entry and click on the Automatic box
to display the Automatic Global Route form.
Click on the Use Stub Routing button so that the form is as
shown below
Stub Routing allows two cells to be connected without using any channel area
OK the Automatic Global Route form.
OK the Global Route Method form
Check the CIW for status information. A number of warnings will occur but the process will have been successful if the final entry indicates "faults = 0" and the display now resembles that shown below.
Detailed Routing
The Detailed Router implements the actual routing assigned by the Global router and compacts the channels for minimum silicon area.
Select Route - Detail Route - Automatic to display the Route And Compact All Channels form
Click on the pushed button so that the form is as shown below
Locate the "Options" entry and click on the Compact box to
display the Compact Channels form
Set the routing Snap Grid to 0.5 and de-select the Align Formal
Pins button as shown below
The Routing Snap Grid is defined as 0.5 um for the Mietec
process
The Align formal pins option relates to the movement of pins
on sub blocks
OK the Compact Channels form
OK the Route And Compact All Channels form
Check the status imformation in the CIW. Again it is likely that warnings will be issued but a successful routing will produce a final "faults = 0" message and a display similar to that shown below
The layout details can be inspected using the Window - Zoom In option in the autoLayout window.
Click the left mouse button at the top left of the area to be enlarged, drag the cursor to the bottom right of the area and click again.
Save the layout by selecting Design - Save
FINAL DESIGN CHECKS
Before submission for fabrication the design must be checked for compliance with the process design rules. A final post layout simulation incorporating the additional interconnect delays must also be performed over the operating range of the fabrication process.
Performing the Design Rule Check
Before the mask artwork can be generated it is necessary to check that the layout conforms to the process design rules. This is known as a Design Rule Check (DRC).
Select Tools - Layout and observe that an additional Verify option has been added to the toolbar
Select Verify - DRC to display the DRC form
OK the form
Upon completion of the DRC, check the CIW to confirm that no errors have been found
Extracting the Interconnect Delays
Once the layout is complete the additional delay due to the metal interconnect between the components can be extracted for use in a post layout simulation.
Select Tools - Floorplan/P&R - Cell Ensemble to re-display the layout window.
Select Analyse - Mietec 2um CMOS - Extract Parasistic Capacitance
from the layout window
An Extract Wiring Length message will appear
Click on OK to select all nets and to create an empty delay
file (sim.cap)
A File Exists message will now appear
Click on OK to replace the empty file with delay information
Performing a Post Layout Simulation
The gate level simulation can now be re-run with the added interconnect delays.
Select Mietec 2um CMOS - Top Flow Browser from the CIW toolbar to display the Top Level Design Flow menu.
Double click on the Semi-Custom Design button to display
the Semi-Custom Design Flow.
This menu, designed by RAL, provides an alternative means
of moving through the design flow.
Double click in the Post Layout Simulation box to display the Design Entry Form
Enter smotor for the Library Name, chip for the Cell Name
and schematic for the View Name
OK the form
The usual Verilog-XL Integration Control menu will appear and the chip schematic will open
The post layout simulation runs from a different simulation directory (verilog.chip.run1). The existing test pattern file testfixture.new will have to be copied to this directory
Select Stimulus - Verilog and select Yes to create a testfixture
file and open the Stimulus Options form
Click on the Copy button
To copy the testfixture file it will be necessary to move
up a directory and across into chip.run
Click on the directory upwards symbol ../ at the top of the
file list to display the contents of smotor
Now scroll down the file list to locate the chip.run1 directory
and select
Check that the File Names in the Copy From: and Copy To sections
are set to testfixture.new
Activate the Make Current Test Fixture button then OK the
form
Remove the +dlverbose option from the verilog Setup - Simulation - Simulation Options - More form
Run the simulation as normal. Display the waveforms. Measure the new propagation delay of the signal you noted earlier and observe that the value is now greater.
Close the DAI Signalscan Waveform and Design Browser windows
Tolerancing the Design
All simulations so far have been run with nominal propagtion delays obtained at room temperature and recommended power supply voltage. In order to ensure that the design will work properly across the entire operating range of the process the design can be simulated at worst and best cases of temperature and power supply voltage. This is achieved by re-running the simulation with the nominal propagation delays multiplied by a suitable scaling factor for each case.
Select Setup - Simulation from the Verilog-XL Integration Control menu to display the Simulation Options form. Locate the Delay section and observe that the current Type setting is Typical
Activate the Minimum button and OK the form
Re-run the simulation, display the waveforms and check for correct functionality. Measure the timing of the signal you previously noted in the post simulation exercise. The delay should be shorter.
Close the DAI Signalscan Waveform and Design Browser windows
Repeat the above process setting the simulation delay to Maximum. Again check for correct functionality and observe that the propagation delay of the noted signal is now longer.
Close the DAI Signalscan Waveform and Design Browser windows
Leaving CADENCE
Select System - Return on the Semi-Custom Design Flow
menu toreturn to the Top level Design Flow
menu
Select System - Close on the Top level Design Flow
menu to close the menu
Close the Verilog - XL Integration Control menu
Close the schematic window
Select File - Exit on the CIW to exit CADENCE.
The message "OK to exit icfb?" will be displayed. Select Yes to complete the exit operation.