Analogue and Mixed Signal Integrated Circuit Design
Unit 2: Amplifier Design Techniques
Unit Contents
- 2.1 Review of Amplification Fundamentals
- 2.2 PNP Transistors and Active Loads
- 2.3 Gain of a Differential Pair with Active Loads
- 2.4 Buffer Stage
- 2.5 Towards a Practical Amplifier Design
- 2.6 Stability Issues
2.1 Review of Amplification Fundamentals
Figure 1 shows a simple common-emitter BJT amplifier in which the transistor is biased at IC amps. (The biasing circuit is not shown).
Figure 1: A simple common-emitter BJT amplifier
The gain of this circuit, vout/vin, is just gmRL volts/volt. Using the result from Unit 1, we know that this is equal to (IC/VT)RL which is in turn equal to 38.5 ICRL at 27 degrees Celsius. The rule of thumb for this type of circuit is that the voltage gain is given by approximately forty times the dc voltage across the collector load resistor. This calculation does not take into account the slope resistance of the transistor itself, which is assumed to be much higher than the value of the load resistor.
For example, if we have a 12-volt supply, the collector might be biased at
6 volts dc. The voltage gain obtained might be a little under 240 volts/volt.
This is not a very large number and represents the absolute maximum gain that
can be achieved and takes no account of the effects of finite input resistance
and loading of the output by the next stage.
How are we to increase the voltage gain then? We can certainly increase the
collector current and increase the value of load resistor but changing either
of these values will disturb the bias point from the 6 volts dc that we would
like. It turns out that there is really no answer to the problem: it is not
possible to get respectable voltage gain from an NPN-only gain stage without
resorting to very high supply voltages, whereas the modern trend is to ever
lower supply voltages.
Figure 2: The Differential Case
Figure 2 represents the differential case where vout(diff)/vin(diff) is again gmRL. In some circumstances, though, the situation in Figure 2 can be even worse. There is a common need for a stage that accepts a differential input and gives a single-ended output (for example at the front end of an operational amplifier). When we take the output from only one side of the differential pair, the gain is reduced by half to (gmRL)/2.
Despite these difficulties, much higher gains than this can be obtained from a single stage but to do so calls for active loads constructed from PNP transistors which is outlined in the next section.
2.2 PNP Transistors and Active Loads
There are a variety of techniques for constructing PNP transistors on the same chip as NPN ones. Ideally, a designer would like the PNP devices to have similar properties to the NPN ones but this is rarely achieved.
The lateral PNP comes for free with a standard analogue bipolar process
but you only get what you pay for. An NPN transistor is a vertical device with
collector, base, and then emitter, sandwiched on top of each other. The base
width is a key dimension and defines current gain (BF). BF will be usefully
high as long as the base region is thin (but not too thin, when collector-emitter
short circuits could result).
The lateral PNP has its collector and emitter regions side by side with a wide
base region in between. It is just not possible to define this lateral base
width with the same precision and accuracy as for the vertical base of an NPN
device. The thick base of a lateral PNP produces a device which exhibits low
current gain and poor high frequency performance. (The previous discussion
is something of a simplification. The doping level of the lateral PNP 'emitter' is
also too high and this, too, detracts from the performance obtained.) Despite
the serious problems associated with lateral PNPs, they are still extremely
useful devices because they enable PNP current sources to be fabricated.
With the advent, in the last five to ten years, of more sophisticated processing techniques, including ion implantation, it has become possible to consider the fabrication of vertical PNPs. At the cost of increased process complexity it is feasible to obtain PNP devices with greatly improved frequency and current gain performance but even then they will tend to fall short of NPN performance in a number of important areas. As an example, a vertical PNP will usually have a much lower current handling capacity than its NPN counterpart. Vertical PNPs are always preferable, if available, but either type can be used to produce PNP active loads in gain stages.
Figure 3: Figure 2 re-drawn, load resistors replaced by a PNP current mirror
Figure 3 shows the stage of Figure 2 re-drawn, with the load resistors replaced by a PNP current mirror. There are three major advantages resulting from this arrangement:
- The output of a current mirror, when used as an active load, will have a much higher slope resistance than a resistor, which will lead to higher voltage gain.
- Use of a resistor implies a significant dc voltage across it (e.g. 6v dc is needed for 220+ gain) whereas a current mirror can operate over a wide range of output voltages and, in particular, to within 200mV or so of the supply rail. This suggests that active loads might be used successfully in high gain circuits that are required to operate with only a low supply voltage (and this indeed turns out to be the case).
- Although the PNP mirror can only give a single ended output, the change in current in the left-hand side of the circuit is not wasted because it is mirrored into the output side. Compare this with the single ended output where resistive loads have been used: in that case, the collector of Q1 might as well be taken directly to the supply rail - there is no point developing a signal across a resistor if it is never used.
2.3. Gain of a Differential Pair with Active Loads
You will recall that the gain of the resistor-based differential pair was
gmRL. As suggested above, this was something of a simplification,
as the output resistance of the transistor should have been taken into account.
The effective load resistance is given
by RL in parallel with VAF/IC (the output resistance of
the transistor).
In the case of active loads, the effective load resistance is the parallel combination
of the output resistances of the PNP current mirror device and the NPN device
in the differential pair. For a given collector current, transistor output resistance
is proportional to VAF and you might suspect (correctly) that there is some relationship
which states that high VAF leads to high gain.
The theory is fully developed in Gray and Meyer but the key equation is (4.96):
Voltage gain = 1/[(VT/VAN) + (VT/VAP)] where
VAN and VAP are the Early voltages of the NPN and PNP
device respectively.
It is very clear that changing the bias current of such a stage has no effect
on the voltage gain but it does increase the bandwidth while reducing the input
and output resistances. Normally the collector currents in the front end of
a bipolar differential amplifier are kept low to ensure that the base currents
(i.e. the amplifier input bias currents) are also kept low.
Self Assessment Questions
Question 1
What is the voltage gain of the circuit in Figure 3?
Interactive Spice Simulation Exercise 1
Note: open loop evaluation of amplifiers is very difficult on the bench, especially if high gains are involved but open loop simulation of amplifiers is straightforward and is a very useful technique.
Use Cadence to schematically capture and simulate the circuit of Figure 3. Set Vcc=5 volts and use a 100uA current source for the tail current. Because the amplifier has a single supply, it is necessary to define a pseudo-ground at 2.5 volts d.c. which can be applied to the right-hand input of the amplifier. A second voltage source can then be used to apply a differential input (d.c. and a.c.).
- By means of a d.c. sweep (or otherwise) find the small differential d.c. input that must be applied to force the collector voltages to be more or less equal (4.3 volts approx.).
- With the d.c. offset found from (i) still in place, apply 10 mV a.c. to find the low-frequency a.c. voltage gain. Compare this figure with the answer from SAQ1.
2.4 Buffer Stages
At some point it will be necessary to buffer the output from a differential gain stage with active loads. The whole point of such a stage is that the output resistance is very high - that's where the high gain comes from, as discussed above. Buffering can multiply the available output current by 100, or even 10,000 depending on the circuit, while reducing the output resistance by the same amount. The effective output resistance can then be reduced even further by negative feedback.
Circuits for an emitter follower and two-transistor (Darlington) emitter follower are shown in Figure 4.
Figure 4: Circuits for an emitter follower and two-transistor (Darlington) emitter
The load can be a resistor but is more typically a current source. RB is optional but is used to avoid a large RC time constant at the base of Q2 which might arise if current gains are to the high end of any processing spread.
2.5 Towards a Practical Amplifier Design
Figure 5: A "basic" operational amplifier
The amplifier in Figure 5 acts like an operational amplifier with a voltage gain of approximately 20,000, depending on Early voltage and current gain values. It consists of two gain stages (differential and then single-ended), followed by an emitter follower buffer stage.
This circuit has a number of advantages:
- Relatively simple design.
- Assuming good transistor matching, the circuit itself does not introduce any appreciable input offset voltage.
- Low input bias current.
There are also disadvantages and limitations:
- Some effort has gone into obtaining high voltage gain from the very first stage but driving the 2nd stage directly, without buffering the signal in any way, dissipates that advantage. In other words, the un-buffered 2nd stage input attenuates the 1st stage.
- A single emitter-follower output buffer would not be enough to drive an output off-chip (but it could still be useful at the lower current levels on-chip).
The amplifier will normally be used with negative feedback. But, as it stands, its frequency response will not be suitable for this purpose (as discussed in the next section) and oscillation and instability will result.
2.6 Stability Issues
2.6.1 Introduction
A full discussion of operational amplifier stability is beyond the scope of this course and involves a lot of mathematical control theory. The purpose of this section is to briefly outline the fundamental problem that arises when an amplifier of limited bandwidth is used with a large amount of negative feedback. The discussion will go on to explain the classical "dominant pole" technique that has been used so successfully in amplifiers like the 741 and can equally be applied to any analogue IC design.
An operational amplifier (either a commercial one or the 'basic' one in Figure 5) can be represented by Figure 6.
Figure 6: Representation of an operational amplifier
This shows three gain stages, A1, A2 and A3. A3 is normally a buffer with a gain of one. At low frequencies there is (by definition) a 180 degree phase shift between the inverting input and the output with no phase shift between the other input and the output.
The overall frequency response can be modelled quite well by assuming each
stage's individual frequency response is limited by a CR time constant. Normally
each successive stage runs at a higher current then the previous one, thus:
C1R1 > C2R2 > C3R3
Each CR can introduce a maximum of a 90-degree lagging phase shift. At some frequency the first stage will contribute a phase shift approaching 90 degrees and at higher frequencies this will also be true of the 2nd and 3rd stages too. Potentially all three stages together can cause an excess phase shift of up to 270 degrees. But long before that happens, the excess phase shift will reach 180 degrees, or to put it another way, the phase shift between the inverting input and output will be increased from -180degrees to -360 degrees.
Figure 7: A voltage follower amplifier with 100% negative feedback
What is intended as negative feedback will become positive when the excess phase shift in the amplifier exceeds 180 degrees.
Figure 7 shows a voltage follower amplifier with 100% negative feedback. The low frequency -180 degrees phase shift is intentional to provide negative feedback. If there is a further -180 degrees of phase shift, introduced by the amplifier itself, instability will result if the open-loop gain of the amplifier is still >= 1 at that point.
There are a number of figures-of-merit to summarise amplifier stability. One of the most useful is the concept of "phase margin". As an example, assume that the open-loop gain has fallen to exactly 1 and that the phase shift between inverting input and output is now -300 degrees. This will imply a phase margin of 60 degrees which is acceptable in many situations.
2.6.2 Dominant Pole Technique
Figure 8: A modified version of Figure 6
A2 is an inverting amplifier and multiplies C by a factor of (1 + A2)
Figure 8 is a modified version of Figure 6. "C" represents a small capacitor, between 10 and 30 pF, which is connected between the input and output of the A2 stage. This has the outcome of increasing the effective value of C to (1 + A2).C due to Miller multiplication.
Imagine that the 2nd stage gain is as little as a thousand (and it may well be more). The result is that a small 10pF capacitor on the chip behaves like 10nF hung on the output of the first stage. The cut-off frequency of the first stage is now very low and its gain falls rapidly, becoming very much less than one before the CR time constants of A2 and A3 "kick in". (Even if the 2nd stage pole does start to contribute to the amplifier role-off, it will then reduce the effective value of the capacitor hung on A1 - which depends on the gain of the A2 stage. Thus the A1 and A2 poles acting together still operate as a single pole in many ways. The A2 pole does not operate in its own right until a much higher frequency than it would without the presence of the Miller capacitor. This effect is known as pole-splitting. There is a more rigorous treatment of this in G&M page 616).
Ideally, the overall gain of the amplifier will have been reduced to less than one entirely due to the dominant CR or "dominant pole" of the first stage, with only 90 degrees of excess phase shift having been introduced.
Operational amplifiers based on internal dominant pole compensation are unconditionally stable but there is a price for this stability. The amplifier bandwidth is greatly decreased: the open-loop frequency response starts to roll off at a few Hz. In the case of a 741, the low bandwidth and limited slew-rate restrict the amplifier to applications involving frequencies even lower than audio (< 10kHz). A 741 is most suited to low frequency applications down to dc.
Interactive Spice Simulation Exercise 2
Refer to the circuit in figure 5.
Set Vcc = 5 volts with V+ = 2.5 volts. Change the area parameter of the 2nd stage PNP to two.
- Find the small d.c. offset (applied between V- and V+) that will force the amplifier output to 2.5 volts.
- Perform an a.c. simulation from 1Hz to 1GHz and confirm that there is very little phase margin (if any).
- Apply a small compensation capacitor. (This will work best if taken from the 1st stage output to the output pin). Find the value of capacitor that gives 60 degrees phase margin.
Further Study
Students are referred to Unit 4.3 and Unit 9 of Gray and Meyer.