Layout for Analogue and Mixed Signal Design
This module is under development.
Introduction
Digital engineers can, and do, operate with no knowledge of the underlying physical structures and processes utilised. In contrast, it is impossible to be an effective analogue or RF design engineer without a comprehensive understanding of the theoretical device characteristics and the physical aspects and interactions of the structures produced and used on the chip.
Layout is an important part of analogue ASIC design. Analogue engineers will routinely perform layout operations themselves, or provide instructions to layout engineers. The devices used, and their structures, have a significant impact on the performance of the design, so the ability to interpret ASIC design rules and process parameters and understand their impact on physical structures is an important aspect of the analogue engineer’s role.
Module Overview
This module is intended to provide students with the ability to interpret design rules and to be able to produce “good” layouts for various macro classes. The intention is for the students to be able to analyse, implement and layout analogue macros utilising “best practice” techniques for a given process. The module includes aspects of layout design relating to structures, matching, tolerances, thermal and electrical issues, and issues specific to DSM and high frequency design.
The subject is developed using a large number of tutorial layouts and layout/schematics. This ensures that students gain actual experience of creating the relevant structures, of debugging them and tracking down errors and issues. Some of the errors will have been introduced deliberately, giving students the opportunity to build their own set of “FAQs” when they encounter similar errors in their own constructions. It is intended that all exercises will be based on the AMS 0.35um, 4 layer metal design kit revision 3.60 or 3.70.
Contents
- Introduction to layout
- Implementing devices
- How the layers combine
- Design rules
- Layout
- Drawing the layout
- PCells/ROD and vias
- Checking the result
Suggested Study Plan
| Study Week | Unit | Unit / Assessment |
|---|---|---|
| 1 | 1 | details to follow |
| 2 | ||
| etc |
Tutor and Author Profiles
| Neil Cole | |
|---|---|
 |
Neil has 22 years industrial experience in semiconductor design. For the past three years he was CAD manager for a multinational semiconductor design house working on mixed signal system on chip platforms. His background includes extensive design experience on DSM CMOS, FPGA, BiCMOS and bipolar technologies from specification onto final test. He has worked on SOC and mixed signal design flow development and implementation for a variety of companies. Areas of interest include SOC platform, tool and design flow development, in particular with regard to the simulation and test of large mixed signal designs, using analogue HDL, mixed environment or digital simulators. In addition to tutoring e-learning modules, he is responsible for co-ordinating technical support for remote access by students studying through Bolton. |
Recommended Textbook
| Title | Author | ISBN | Publisher | Date |
|---|---|---|---|---|
| CMOS IC Layout | Dan Clien | available online via Athens authenticated access from the university. | ||
| CMOS VLSI Design, A Circuits and Systems Perspective | Weste and Harris | |||
| CMOS Circuit Design, Layout and Simulation | Baker, Li and Boyce |
Updated 17.10.07 RA