Advanced Electronic Design Automation
Module Overview
Three examples of high level tools are covered
- Circuit Simulators (SPICE) - Required to verify correct functionality
of hand crafted digital and analogue cells
- Behavioural and Structural Logic Simulators (VHDL and Verilog) - Required
to define, simulate and synthesise digital circuits
- Fault Simulators (VERIFAULT) - Required to develop test patterns and determine testability of digital circuits
Principles of operation are detailed in the teaching material and practical CAD tool exercises provide competence in their utilisation.
Expertise and competence in the utilisation of Computer Aided Design tools are essential requirements for implementing the integrated circuit design flow. The two design orientated modules Digital Integrated Circuit Design and Analogue and Mixed Signal Integrated Circuit Design contain substantial design projects which will require the deployment of these tools. A comprehensive introduction to the use and operation of a set of tools appropriate to a given process and technology will be provided in these modules.
Generally most tools demand sufficient knowledge only at this operational level for their execution. There exists however a group of tools that require significant supplementary expertise before they can be successfully utilised. These we have classified as high level tools and are dealt with in this module as a necessary prerequisite for their subsequent application in the design modules.
Contents
- Unit 1: Introduction to electronic design automation & SPICE concepts (inc. SPICE exercises 1 - 3)
- Unit 2: Semiconductor modelling in SPICE (inc. SPICE exercises 4-6)
- Assignment 1 (SPICE) 15 hours, worth 30%
- Unit 3: Fault simulation and test pattern generation (inc. Verifault exercises 1-2)
- Unit 4: Introduction to VHDL
- Unit 5: Elements of VHDL (inc. VHDL exercise 1)
- Unit 6: Describing digital systems using VHDL (inc. VHDL exercise 2)
- Unit 7: Hierarchy, regularity and an introduction to test benches
- Unit 8: VHDL for synthesis (inc. VHDL synthesis exercise)
- Unit 9: From VHDL to Verilog-HDL (inc. Verilog exercise)
- Assignment 2 (VHDL/Verilog) 35 hours, worth 70%
Reference Material
Suggested Study Plan
| Study Week | Unit | Unit / Assessment |
|---|---|---|
| 1 | 1 | Introduction to Electronic Design Automation and SPICE concepts (includes SPICE exercises 1-3) |
| 2 | 2 | Semiconductor modelling in SPICE (includes SPICE exercises 4-6) |
| 3 | SPICE assignment, 15 hours (worth 30%) | |
| 4 | 3 | Fault simulation and test pattern generation (includes Verifault exercises 1-2) |
| 5 | 4 | Introduction to VHDL |
| 6 | 5 | Elements of VHDL (includes VHDL exercise 1) |
| 7 | 6 | Describing digital systems using VHDL (includes VHDL exercise 2) |
| 8 | 7 | Hierarchy, regularity and an introduction to test benches |
| 9 | 8 | VHDL for synthesis (includes VHDL synthesis exercise) |
| 10 | 9 | Verilog (includes Verilog exercise) |
| 11&12 | Assignment 2 (VHDL / Verilog), 35 hours (worth 70%) |
Tutor and Author Profiles
| Jeff Ormerod - Tutor and author of units 1 - 3 and Assignment 1 | |
|---|---|
 |
A profile of Jeff Ormerod is to be found in the overview for Microelectronic Technologies and Applications. |
| Neil Cole - Tutor for units 4 - 9 and Assignment 2 | |
 |
Neil has 22 years industrial experience in semiconductor design. For the past three years he was CAD manager for a multinational semiconductor design house working on mixed signal system on chip platforms. His background includes extensive design experience on DSM CMOS, FPGA, BiCMOS and bipolar technologies from specification onto final test. He has worked on SOC and mixed signal design flow development and implementation for a variety of companies. Areas of interest include SOC platform, tool and design flow development, in particular with regard to the simulation and test of large mixed signal designs, using analogue HDL, mixed environment or digital simulators. In addition to tutoring e-learning modules, he is responsible for co-ordinating technical support for remote access by students studying through Bolton. |
| Ian Elliott - Author of units 4 - 9 | |
 |
Ian Elliot is a Senior Lecturer at Northumbria University, where he teaches VLSI Design, Advanced Digital Systems Design and Microprocessor Systems. He has maintained links with industry through consultancy and training activities and has also developed and taught a number of short courses for industrial clients in the area of programmable logic design using hardware description languages. His research interests include design for test, having published a number of papers in this area. He is a chartered engineer and member of the Institution of Electrical Engineers. |
Recommended Textbooks
Units 1 - 2
| Title | Author | ISBN | Publisher |
|---|---|---|---|
| Application Specific Integrated Circuits | M.J. Smith | 0-471-98325-X | Addison Wesley |
| The Spice Book |
A. Vladimirescu | 0-471-60926-9 | John Wiley & Sons |
Units 4 - 8
| Title | Author | ISBN | Publisher |
|---|---|---|---|
| VHDL for Logic Synthesis, 2nd Edition |
A. Rushton | 0-471-98325X | John Wiley |
Unit 9
| Title | Author | ISBN | Publisher |
|---|---|---|---|
| Modelling, Synthesis and Rapid Prototyping with the Verilog HDL |
M.D. Ciletti | 0-13977-398-3 | Prentice Hall |
| Verilog HDL - A Guide to Digital Design and Synthesis |
S. Palnitkar | 0-13451-675-3 | Prentice Hall |
Updated 24.01.06 RA & JO