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Advanced Electronic Design Automation

Unit 3: Fault Simulation and Test Pattern Generation

This unit introduces the concepts of ASIC testing. The utilisation of fault simulators both in assessing the testability of designs and in formulating test pattern sets is discussed. Practical exercises using the Verifault fault simulator within CADENCE are also included.

Unit Contents

• 3.1 The Need for Testing
• 3.2 Role of the Fault Simulator
• 3.3 Fault Simulator Operation
• 3.4 Fault Simulation in the Design Process
• 3.5 Basic Testing Concepts
  • 3.5.1 The SA0 and SA1 Fault Model
  • 3.5.2 Controllabilty and Observability
  • 3.5.3 Fault Categories
  • 3.5.4 Fault Simulation
  • SAQ and associated Verifault Exercise 1
• 3.6 Test pattern Generation
  • SAQ and associated Verifault Exercise 2
• 3.7 Fault Simulation of Sequential Circuits
• 3.8 Behavioural Fault Simulation

3.1 The Need for Testing

The modern integrated circuit is a complex device manufactured by a complicated fabrication process. At any stage in the process physical defects can occur in the silicon which can render the resultant device useless.

Transistor construction can be flawed, metal tracks can be shorted or open circuit, die can be damaged during wafer sawing or packaging and human error or mechanical failure can result in a processing step being incorrectly implemented. For this reason ICs are tested twice during manufacture.

The first test occurs at the completion of fabrication. Each die is subjected to a Wafer Test during which a series of test patterns are applied to the input bond pads by wafer probes and the resulting signals on the output bond pads captured for analysis.

A second test occurs when the devices have been packaged, often using the same set of test patterns.

Customers may also test the devices prior to and after assembly into a product.

Failure to detect even a small percentage of faults can be costly. The designer must therefore supply a comprehensive set of test patterns capable of identifying every possible fault that can occur in the device.

3.2 The Role of the Fault Simulator

An initial set of patterns would typically be those developed during the simulation phase of the design process. These patterns, however, are primarily intended to test for design errors and will not necessarily detect all manufacturing defects.

A fault simulator enables the designer to assess the efficiency of this initial set and assists in the development of additional patterns such that all possible faults can be detected. The resulting effectiveness of a test pattern set is referred to as the Fault Cover and is expressed as a percentage of the detected faults with respect to the detectable faults. The goal is therefore to achieve a 100% fault cover.

Often a circuit may be required to function in such a way that makes it impossible to detect certain faults with any test pattern. In these circumstances it is necessary to incorporate additional test circuitry for the purpose of achieving maximum fault cover. This is known as Design for Testability. A good fault simulator will also identify these undetectable faults and assist the designer in the development of appropriate test logic.

It is also possible to automate to a certain extent the production of a test pattern set using an Automatic Test Pattern Generator which analyses the faults that can occur in the circuit logic and generates the appropriate patterns. These patterns can then be applied to the circuit by the fault simulator and the resulting fault cover determined.

3.3 Fault Simulator Operation

There are a number of fault simulator algorithms. All operate on the principle of performing a normal simulation (the good circuit) and capturing the outputs. The circuit is then re-simulated with a series of faults injected (the faulty circuit) and the outputs compared.

Serial Fault Simulation  involves simulating the good circuit, capturing all the output states for each test pattern then simulating the faulty circuit one fault at a time. The process is slow and impractical for large circuits.

Parallel Fault Simulation simulates the good circuit then simulates many faulty circuits simultaneously storing the results of an individual output in the bits of the computer word in memory. One bit is used for the good circuit and the remaining bits for the faulty circuits. Other words are used for other outputs. This technique is considerably faster than serial fault simulation.

Concurrent Fault Simulation operates on the principle that not all of the circuit needs to be simulated in order to detect a particular fault. As before, the good circuit is simulated then only the appropriate part of the faulty circuit for each fault. The simulation algorithm is more complicated but the resulting speed of execution is much faster. The Verifault fault simulator uses the concurrent technique.

There are also a number of Simulation Engines or Hardware Accelerators on the market that exploit the performance advantages of using dedicated hardware rather than software to perform parallel fault simulation.

3.4 Fault Simulation in the Design Process

The necessity to consider testing as an essential element in the design activity has led to the integration of fault simulators within the design process.

A circuit will have been entered either schematically by a schematic capture package or structurally by a hardware description language such as VHDL or Verilog. Fault simulators can only operate at the structural level (although some like Verifault are capable of propagating faults through behavioural descriptions). Circuits initially defined at the behavioural level must first be synthesised to a particular target technology.

The circuit will then be functionally simulated using a set of test vectors designed to verify the circuit in all its operating modes.

A correctly functioning circuit can then be fault simulated using the same test vector file developed during functional simulation. It is usually necessary to incorporate additional commands into this file to specify the type and nature of faults to be injected and strobe information relating to the points in time when outputs can be inspected.

The result of the fault simulation is a Fault Dictionary detailing the faults that can be detected in the circuit and a Faults List which reports on the faults actually detected/undetected by the test patterns.

Typically this first pass could result in fault covers of around 60% being attained. The information in the fault list relating to the undetected faults can be used to enhance the test patterns and the process repeated  until full fault cover is achieved. This may also involve modifications to the design to improve testability.

3.5 Basic Testing Concepts

The range of defects likely to be introduced during the fabrication process is immensely varied. A fault model that could handle all possibilities would be extremely complex and unworkable. Fortunately experience has shown that whatever the cause of the fault the effect is likely to be an input/output pin (port) or a wire (net) or a component pin (terminal) either stuck permanently at a logic 0 (SA0) or stuck permanently at a logic 1 (SA1). All fault simulators operate on variations of this basic fault model.

3.5.1 The SA0 and SA1 Fault Model

Consider the following circuit in which the AND gate output is stuck at 0.

A Circuit

We can define two truth tables, one for the circuit working correctly and one for the circuit with the fault.

We observe that the input pattern A=1, B=1, C=1 produces a difference at the output between the expected value in a good circuit and the actual value obtained in the faulty circuit. A tester operating on this circuit will know the expected value, measure the actual value, compare the two and detect the fault.

3.5.2 Controllabilty and Observability

Test patterns can only be applied at the input pins to integrated circuits and faults observed at the output pins.

Therefore when determining a suitable combination of input values for a test pattern it is necessary to consider both how a particular fault can be set up from the inputs (Controllability) and seen at the outputs (Observability).

The previous example shows that values on A and B that would produce a logic 0 on the AND gate output or values of C that would force the OR gate output to logic 1 are ineffective in detecting the fault. We conclude therefore that in order to detect the fault it is necessary to attempt to set the faulty node to a logic 1 (i.e. the opposite logic value to the stuck-at fault) by setting A=1, B=1 and to ensure that the fault is not obstructed from being seen at the output by setting C=1. The process of clearing an observable route to an appropriate output is referred to as Sensitising a Path.

3.5.3 Fault Categories

Four types of fault are typically identified by fault simulators:

Detected faults are those that can be detected and have been detected by one or more test patterns. These faults are flagged when a value observed on the faulty circuit is different to that of the good circuit.

Undetected faults are those that can be detected but have not been detected by any of the test patterns. These faults are flagged when a value observed on the faulty circuit is the same as that of the good circuit.

Potentially Detected faults are those that can be detected but only might have been detected. These faults are flagged when a value observed on the faulty circuit is indeterminate (X) whilst that of the good circuit is 0 or 1.

Example:

Example Circuit

In a good circuit the RESET signal would be capable of initialising the flip flop to a known state and therefore defining a known value on F. In the faulty circuit, however, a SA1 fault on the RESET would prevent the flip flop from being initialised correctly and the resulting output would therefore be unknown (i.e. either a 0 or a 1). Whether or not the fault is detected would depend on this unknown value being the same or different to that defined for the good circuit. We cannot say for certain that the fault is detected but it may be so we classify it as being Potentially Detected.

These type of faults are included in the analysis because usually as testing proceeds one or more test patterns will eventually reveal a discrepancy between the good and bad circuits and the fault will be detected. 

Untestable faults occur on nets that cannot be controlled or nets that cannot be observed

Example:

Example Circuit

A fault on the flip flop NQ output cannot be detected since it cannot be observed at any of the circuit outputs. Similarly a fault on the input of the AND gate tied to VDD to define a logic 1 cannot be detected since it cannot be controlled by the simulator to the required logic values.

The Verifault fault simulator used in CADENCE will identify untestable faults in circuits and determine detectable, undetectable and potentially detectable faults according to the following model.

Where:

Z = High Impedance 
X = Unknown 
L = 0 OR Z 
H = 1 OR Z 
D = Detected 
U = Undetected 
P = Potentially Detected

3.5.4 Fault Simulation

Typically in logic circuits a particular test pattern in a set will detect a number of faults.

Example:

Example Circuit

To test for a SA0 on F we need to set A=1 and B=1.
To test for a SA0 on A we also need to set A=1 and B=1.

We say that these two faults are Equivalent Faults such that if the fault simulator can detect one of them it can also detect the other.

Additionally a fault that can occur on a net will be the same fault as that on the logic element terminal to which it is connected or to the circuit port which it drives or is driven by.

We can therefore collapse all possible faults on ports, nets and terminals to a small set of Prime Faults to which all other faults are equivalents.

3.6 Test Pattern Generation

For logic circuits with any degree of complexity it would be uneconomical both in terms of redundancy and testing time to construct a test pattern set that consisted of all possible input signal combinations even though this would give the best chance of achieving full fault cover.

Consider the following adder circuit constructed internally from 8 cascaded full adders :-

Adder Circuit

A comprehensive test for correct functionality would require  256 values on A and 256 values on B each with both values of CARRY IN giving a total of 256 x 256 x 2  = 131,072 combinations.

In reality a functional simulation would specify only a small fraction of these values. The designer would carefully choose a set of patterns to test the circuit in all its possible operating modes.

Typical patterns would include a range of positive and negative numbers with and without the CARRY IN signal, bit patterns with alternate 1s and 0s to check that each full adder had been wired correctly, worst case carry conditions to check that a CARRY IN will ripple successfully from the least significant to the most significant stage etc.

Applying this functional set of test patterns to a fault simulator could be expected to deliver a reasonable degree of fault cover (typically around 60%). The simulator will produce a faults list that will identify the type and nature of the undetected faults. The designer can then use this information to devise additional test patterns and re-simulate. This process will be repeated until maximum fault cover is achieved.

3.7 Fault Simulation of Sequential Circuits

In addition to the logic faults already considered for combinational circuits, sequential circuits are also susceptible to Parametric faults which can effect voltage and current levels and switching speeds. They arise from improper fabrication or the normal aging process often accelerated by extremes of temperature, humidity or mechanical vibration. The result can be timing variations and consequent circuit failure. Typical faults likely to occur are Race Conditions where two or more signals change simultaneously and Hazards where a signal momentarily changes value (a Glitch).

In determining a suitable set of test patterns for sequential circuits, particular attention has to be paid to the order in which test vectors are applied.

Example:

A SET-RESET flip flop

The circuit defines a SET-RESET flip flop and its associated truth table.

Testing for each of the NAND gate inputs SA1 using the SET/RESET input values sequenced as in the truth table produces the following results on the Q output.

This sequence of patterns is effective in detecting all faults except where in all input combinations the good circuit and the faulty circuit outputs are identical.

Running the input sequence in reverse produces the following results:-
 
 

Now some of the outputs are indeterminate as a result of the ordering of the sequence. For example the first combination of inputs would normally retain the current value of Q but that value has not been defined.

These indeterminate values may ultimately be classed as potentially detected faults, but with only the fault actually detected the overall fault cover is lower than before.

A further complication can arise if the input pattern 0,0 is followed by the pattern 1,1. The first pattern can force both outputs to logic 1, feeding this value back to the NAND gate inputs. Under these conditions the second pattern will force the outputs to logic 0, feeding this value back to switch the outputs back to logic 1 and so on. The circuit therefore oscillates at a frequency determined by the propagation delay of the gates. A fault simulator will identify this type of fault as an Oscillation Fault.

The application of automatic test generators for sequential circuits has proved difficult to achieve and for this reason a high degree of designer involvement in specifying test patterns is required.

3.8 Behavioural Fault Simulation

Fault simulators can only analyse circuits described at the structural level. This implies that any circuit defined behaviourally in VHDL or Verilog must first be synthesised to the required target technology before running the simulator.

Simulators like Verifault also provide the capability to propagate faults through behavioural components in structural circuits. This is useful when attempting to analyse the testability of the structural parts of such circuits.

A full and complete fault simulation is not possible, however, until all components are in structural form.

updated 24.01.06 RA & JO

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