Systems Design using FPGAs
Module Overview
Field Programmable Gate Arrays (FPGAs) are increasingly becoming a critical part of every electronic system design. FPGAs come in many various types and flavours. This module will enable you to select the appropriate device that is right for your design; a step that is vital to guarantee that your design works correctly and functions as you would expect in the entire system. The module will also cover all aspects of the design flow required to implement designs on actual hardware targets.
An overview of programmable logic will be described leading up to a description of FPGAs. The internal architecture of these devices will be covered and what trade offs may need to be considered when selecting a device that will be appropriate for your design. The design flow for an FPGA based project will be discussed which will include the design, simulation, and testing issues that arise when designing a FPGA based system. Also covered will be board level design considerations which will discuss how to deal with the different I/O characteristics of the FPGA device and board layout design decisions. Advanced topics will be discussed which include the use of IP cores, embedded processors, HDL alternatives such as C/C++ and System C, and DSP based design flows.
The module is appropriate for a wide spectrum of engineers including both software and hardware designers; Engineers who are about to embark on a FPGA design or wants to be prepared for one; Engineers who have been involved with a FPGA project in the past will find this a useful refresher.
The module is organised into 12 chapters in total, and will be assessed by two assignments (weightings 30% and 70%). It is important that you start the assignments early, as indicated in the suggested study plan. Most units contain relevant SAQ's, answers, and worked solutions. You are advised to attempt these questions as you study each module before checking the solutions
There are no text books required for this module but you may find some useful reading particularly for the assignments from the books listed at the end of this overview.
The module makes extensive use of the Altera Quartus II Software tools and a provided Altera DE1 development board to carry out the walkthroughs, design exercises and assignments.
If you wish follow the instructions in the link: Software and Hardware Installation to make sure you have access to the necessary software, and the correct installation of the hardware and drivers.
The Altera software supports the most common design entry methods including VHDL, Verilog, and graphical based (schematic). The design entry method we will be using in the walkthroughs and design exercises is Verilog. This language is considered easiest to use for the person with no knowledge of either language. Also a programmer with some C experience (used on other modules) then they would find the constructs used in Verilog more readable. However there is nothing to prevent an experienced VHDL student from completing the assignments using either language of their preference.
A word of caution if you do not complete the walkthroughs and design examples week by week and leave the assignments to the last minute you are unlikely to be able to complete them.
The assignments must be referenced, details of which are included in the assignment descriptors. It is important to realise that internal references are required, that is material used from the module material should be referenced in the assignments.
Module Contents & Suggested Study Plan
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Assessment
The module will be assessed on the completion of two assignments having weights of 30% and 70%.
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Author
Kevan
Smart
Kevan is a Senior Designer within the Technology Design Centre at the University
of Bolton. Over the past ten years he has completed numerous design consultancies
for small companies as part of the UK government (DTI) Electronics Design
programme and the European FUSE initiative. Applications have included audio
metering, sensor conditioning, noise suppression, instrumentation and control
systems, GSM telephony and global positioning devices. His teaching expertise
includes embedded systems and he has supervised a number or projects involving
DSP and micro-controller devices. His research interest is high resolution
ECG monitoring and recording and analysis.
Kevan has more than ten years experience working with higher education,
lecturing in electronics and related subjects at honours degree and MSc
level and supervising projects for BEng and MSc degrees.
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Suggested Reading
Recommended Texts
| Title | Author | ISBN | Publisher | Date |
|---|---|---|---|---|
| Verilog HDL: A guide to digital design and synthesis | Samir Palnitkar | 0-13-044911-3 |
Prentice Hall | 2nd Edition 2003 |
| The Design Warriors Guide to FPGAs | Clive Maxfield | 0-7506-7604-3 |
Newnes | 2004 |
| Designing with FPGAs and CPLDs | Bob Zeidman | 1-57820-112-8 | CMP Books | 2002 |
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Updated 23/10/07 KS