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Systems Design Using FPGAs

Unit 01: Programmable Logic Devices

In digital system design the line between hardware and software is becoming increasingly blurred. Hardware engineers now create a large portion of their new circuits using a programming language such as VHDL or Verilog to design their hardware. This language gives a description of the circuit that can then be targeted to a programmable device such a CPLD or FPGA.

Over the past few years, the density of the average programmable logic device has increased significantly with vendors currently quoting upwards of 300,000 logic cells or logic elements on their top end FPGA devices. However competition between the suppliers of PLDs is extremely fierce and consequently the prices for the devices is falling. With the advantage of incorporating processor cores and peripheral devices on chip many system designers are now choosing this technology to provide a complete system on a single hardware chip.

As the PLD hardware technology advances so does the software tools. There are now developments to raise the abstraction level to allow faster design cycles. Amongst these developments are 'System C', ' Catapult C', 'Impulse C', 'SystemVerilog', 'SystemVHDL', 'Handle-C'. There are also products that now allow designers to create their hardware designs in traditional programming languages like C.

With all these advances the fuzzy line between digital hardware and software means that hardware designers must learn how to write better programs, and software developers must learn how to efficiently utilise programmable logic.

This unit covers the various types of available programmable logic devices. It also covers the overall design process involved with CPLDs and FPGAs.

 

Unit Contents

1.1 Types of Programmable Logic

Programmable logic devices are available in many different types. The current range of devices span from small devices capable of implementing only a handful of logic equations to huge FPGAs that can hold an entire processor core and peripherals. In addition to this incredible difference in size there is also much variation in architecture.

Programmable logic devices can be divided into three distinct architectural groups.

Whilst each of these architectures have there own typical particular application area there is also a certain degree of overlap where there is no clear cut decision as to which is the most appropriate device for a particular application. For example some applications such as address decoding could be implemented in both a CPLD and an FPGA however the implementation within an FPGA would allow this to be implemented along with other functionality. In general any function that can implemented in a smaller device can also be implemented in a more complex device.

Figure 1 PLD Application Overlap

Fig 1 PLD Application Overlap

1.1.1 Simple Programmable Devices SPLDs

SPLDs are the simplest, smallest and least-expensive type of programmable logic device. These devices typically have logic gates laid out in arrays where the interconnection between these arrays are configurable by the user.

The term SPLD covers several types of device:

Figure 2 shows a general structure of an SPLD. The connection link across two wires can either be pre-defined or programmable depending on the type of SPLD.

Figure 2 SPLD Structure

Figure 2 SPLD Structure

 

 
PLAs

These are the most configurable of the SPLDs. They consist of two levels of logic gates, an array of AND gates and an array of OR gates, both arrays of which are user programmable. The structure of a PLA allows any of it's inputs (and the complement of its inputs) to be AND'ed together in the AND plane which will correspond to the product term of its inputs. Also each output of the OR plane can be configured to give the logical sum of any outputs of the AND plane. This structure allows the implementation of logic functions in the sum-of-products form. PLAs are particularly useful for large designs that require many common product terms that can be used by several outputs. This is illustrated in Fig 3 showing that the product term (a&b) is used by both the x and z outputs. The downside of the PLA device is the price of manufacture and speed. This device has two levels of programmable links and signals take a relatively long time to pass through programmable links as opposed to pre-defined ones.

Figure 3 PLA Programmed Device

Figure 3 PLA Programmed Device

PALS

The speed problems associated with the PLA were addressed with the development of the PAL. The advantage of a PAL is that they are faster due to having only a single programmable array. However this limits the number of product terms that can be OR'ed together. Because of this, several variants of the device are produced with different numbers of inputs and outputs, and different sizes of OR gate arrays. Also many PALs support registered or latched outputs therefore if necessary the output can be stored in the flip-flop until the next clock edge and sequential designs can be realised. The structure for such a device is shown in Fig 4.

Figure 4 Typical PAL Structure with Register Outputs

Figure 4 Typical PAL Structure with Register Outputs

SPLDs are often used for address decoding, where they have several clear advantages over the 7400-series TTL parts that they replaced. First is that one chip requires less board area, power, and wiring than several do. Another advantage is that the design inside the chip is flexible, so a change in the logic doesn't require any rewiring of the board. Rather, the decoding logic can be altered by simply replacing that one PLD with another part that has been programmed with the new design.

Most SPLD chips use fuses or non-volatile memory cells such as EPROM, EEPROM, or Flash memory to store the logic design functionality.

1.1.2 Complex Programmable Devices CPLDs

This group covers the middle ground in terms of complexity and density between SPLDs and FPGAs. CPLDs can handle significantly larger designs than SPLDs, but provide less logic than field programmable gate arrays (FPGAs). CPLDs contain several logic blocks, each of which includes eight to 500 macrocells. For most practical purposes, CPLDs can be thought of as multiple SPLDs (plus some programmable interconnect) in a single chip. The typical structure of a CPLD is shown in Fig 5. Each of the 16 logic array blocks shown is the equivalent of one SPLD. However, in an actual CPLD there may be more (or less) than 16 logic array blocks. Also each of these logic array blocks are themselves comprised of macrocells and interconnect wiring, just like an ordinary SPLD.

Figure 5 Typical CPLD Structure

Fig 5 CPLD Structure

The larger size of a CPLD allows you to implement either more logic equations or a more complicated design. Most complex programmable logic devices contain macrocells with a sum-of-product combinatorial logic function and an optional flip-flop. Complex programmable logic devices feature predictable timing characteristics that make them ideal for critical, high-performance control applications. Typically, CPLDs have a shorter and more predictable delay than FPGAs and other programmable logic devices. Because they are inexpensive and require relatively small amounts of power, CPLDs are often used in cost-sensitive, battery-operated portable applications. CPLDs are also used in simple applications such as address decoding.

Because CPLDs can hold larger designs than SPLDs, their potential uses are more varied. They are still sometimes used for simple applications like address decoding, but more often contain high-performance control-logic or complex finite state machines. At the high-end (in terms of numbers of gates), there is also a lot of overlap in potential applications with FPGAs. Traditionally, CPLDs have been chosen over FPGAs whenever high-performance logic is required. Because of its less flexible internal architecture, the delay through a CPLD (measured in nanoseconds) is more predictable and usually shorter.

1.1.3 Field Programmable Logic Arrays FPGAs

Field Programmable Gate Arrays are two dimensional array of logic blocks and flip-flops with a electrically programmable interconnections between logic blocks.

The interconnections consist of electrically programmable switches which is why FPGA differs from Custom ICs, as Custom IC is programmed using integrated circuit fabrication technology to form metal interconnections between logic blocks.

FPGAs can be used to implement just about any hardware design. One common use is to prototype a system that will eventually find its way into an ASIC. However, especially if the product has to be available as soon as possible then there is no reason why the FPGA can't be in the final product. Whether it does or not depends on the balance between development time and costs, and cost of the final device (number of required parts).

Figure 6 illustrates a typical FPGA architecture. There are three key parts of its structure: logic blocks, interconnect, and I/O blocks. The I/O blocks form a ring around the outer edge of the part. Each of these provides individually selectable input, output, or bi-directional access to one of the general-purpose I/O pins on the exterior of the FPGA package. Inside the ring of I/O blocks lies a rectangular array of logic blocks. And connecting logic blocks to logic blocks and I/O blocks to logic blocks is the programmable interconnect wiring.

Figure 6 Typical FPGA Structure

Figure 6 Typical FPGA Structure

The logic blocks within an FPGA can be as small and simple as the macrocells in a PLD (a so-called fine-grained architecture) or larger and more complex (coarse-grained). However, they are never as large as an entire PLD, as the logic blocks of a CPLD are. The logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.

Because of all the extra flip-flops, the architecture of an FPGA is much more flexible than that of a CPLD. This makes FPGAs better in register-heavy and pipelined applications. They are also often used in place of a processor-plus-software solution, particularly where the processing of input data streams must be performed at a very fast pace. In addition, FPGAs are usually denser (more gates in a given area) and cost less than their CPLD cousins, so they are the de facto choice for larger logic designs.

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1.2 Hardware Design and Development

The design process is outlined in Fig 7. There are several elements to the complete design cycle. The design flow comprises, design entry, design synthesis, design implementation, and device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow.

Figure 7 Design Flow

Figure 7 Design Flow

1.2.1 Design Entry

Traditionally hardware design was carried out by schematic capture. However as designs have become more complex this method has become less popular and language based tools are now by far the most preferred method of design entry. The most popular language tools are Verilog and VHDL. These tools allow the description of the hardware's structure and behaviour to be written in a high level textual form prior to compilation and downloading to a hardware target. A major benefit of using HDL tools such as Verilog or VHDL is that a design targeted to a specific manufacturer part can be used to re-target the design to another part, another family, or even another manufacturer.

The process of creating digital logic is not unlike the embedded software development process for a PC or a micro-controller. The main difference between software and hardware design is the way in which the problem is interpreted. In an embedded micro controller application the lines of code are executed in a sequential order; there is one execution path. However with hardware design all the input signals are processed in parallel. Therefore the statements of a hardware description language create structures that are all executed at the same time. Hardware designers must think and program in parallel. Note however that the transfer of signals from registers are usually synchronised to some other signal such as a clock. Fig 8 shows the typical format of a HDL design block and illustrates the parallel nature of the process.

Figure 8 FPGA / HDL Design Block

Figure 8 FPGA / HDL Design Block

1.2.2 Simulation

In a typical design flow, the application developer will simulate the design at multiple stages throughout the design process. The three general simulation stages are:

Behavioural simulation is performed before synthesis stage. May not be able to synthesise to hardware.

Functional simulation is performed after the synthesis stage. Timing and analysis is based on assumed gate and routing delays since the design has not yet been paced or routed.

Timing simulation is performed after design place and route. Based on actual back-annotated timing delays and thus more accurate than functional simulation..

Simulation at these various stages allows the designer to test for problems before going on to the next stage of development.

1.2.3 Synthesis

Synthesis or compilation only begins after a functionally correct representation of the hardware exists. This hardware compilation consists of two distinct steps. First, an intermediate representation of the hardware design is produced. This step is called synthesis and the result is a representation called a netlist. The netlist is device independent, so its contents do not depend on the particulars of the FPGA or CPLD; it is usually stored in a standard format called the Electronic Design Interchange Format (EDIF)

1.2.4 Place and Route

The second step in the translation process is called place & route. This step involves mapping the logical structures described in the netlist onto actual macrocells, interconnections, and input and output pins. This process is similar to the equivalent step in the development of a printed circuit board, and it may likewise allow for either automatic or manual layout optimizations. The result of the place & route process is a bitstream. This name is used generically, despite the fact that each CPLD or FPGA (or family) has its own, usually proprietary, bitstream format. Suffice it to say that the bitstream is the binary data that must be loaded into the FPGA or CPLD to cause that chip to execute a particular hardware design.

1.2.5 Programming

Programming a particular FPGA or CPLD can begin once a bitstream file has been created. This bitstream file contains the configuration pattern for the required design. The process of downloading this bit stream depends on the chips underlying technology. Programmable logic devices are similar to memory devices in that there are several underlying technologies. In fact the same of names are used. The programming technologies are summarised below.

Just like their memory counterparts, PROM and EPROM-based logic devices can only be programmed with the help of a separate piece of lab equipment called a device programmer. On the other hand, many of the devices based on EEPROM or Flash technology are in-circuit programmable. In other words, the additional circuitry that's required to perform device (re)programming is provided within the FPGA or CPLD silicon as well. This makes it possible to erase and re-program the device internals via a JTAG interface or from an on-board embedded processor. (Note, however, that because this additional circuitry takes up space and increases overall chip costs, a few of the programmable logic devices based on EEPROM or Flash still require insertion into a device programmer.)

In addition to non-volatile technologies, there are also programmable logic devices based on SRAM technology. In such cases, the contents of the device are volatile. This has both advantages and disadvantages. The obvious disadvantage is that the internal logic must be reloaded after every system or chip reset. That means you'll need an additional memory chip of some sort in which to hold the bitstream. But it also means that the contents of the logic device can be manipulated on-the-fly. In fact, you could imagine a scenario in which the actual bitstream is reloaded from a remote source (via a network of some sort?), so that the hardware design could be upgraded as easily as software.

 

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SAQ

Attempt to answer these questions by use of the chapter notes and the internet and compare your answers to the given solutions.

 

1. Identify the three categories of PLD

 

2. What are the key differences between FPGAs and CPLDs.

 

3. What are the three main components of an FPGA

 

4. What is the main difference between an FPGA and a Micro-Controller

 

show solutions

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Updated 06/07/2007 KS

 

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