Online Postgraduate Courses for the Electronics Industry

Provided By The University of Bolton

• Home
• About Us
• Questions & Answers
• Courses
• Students
• Links

Useful Tools

Communications IC Architectures

Unit 2: Process Choice for Communications

Unit Contents

• 2.1 Introduction
• 2.1.1 Passive Components
• 2.1.2 Thermal Design
• 2.2 Main Technologies Available for Design
  • 2.2.1 Application Areas
  • 2.2.2 Discrete Transistors
• 2.3 Discrete & Integrated Transistors
• 2.4 Silicon Integrated Circuits in RF
• 2.4.1 Reverse base-emitter junction
• 2.5 Transistor Cross Sections - Comparisons
• 2.6 Silicon-Germanium
• 2.7 Gallium Arsenide
• 2.8 Inductors and Transmission Lines
• 2.9 Stripline Filters
• 2.10 Package Effects
• 2.11 Thermal Issues
• 2.12 Digital Circuitry Requirements

2.1 Introduction

There are many issues that complicate process choice for RF integrated circuits. Primarily, of course, for commercial products, there is the cost of the process. However, even this can be broken down into issues such as the cost of the process per function, and the cost of the overall unit. For example, a portable phone has many design criteria, of which the overriding one, after adequate performance, is cost of the phone. Battery life needs to be competitive with alternatives, since it is a selling point, but actual RF performance is not material to the end user. It must work, and it must have adequate battery lifetime. The end user is unlikely to have any appreciation of noise performance of the front end, or dynamic range of the system. Thus the designer of the equipment has to compromise battery size and life against standby/transmit time, and must carry out all the other design compromises in the best possible way. In many respects, judgements have to be made on the relative merits of some issues, but the fast design turnover suggests that these judgements are being rapidly refined.

At the circuit design level, a very wide range of circuits is required, from low noise, wide dynamic range RF amplifiers and mixers through analogue to digital converters to VLSI decoding chips. Where possible, software reconfigurability is desirable, and overall system cost is paramount. Thus the design of chips for cellular phones is determined primarily by unit cost. Heavy initial investment in design is acceptable provided it leads to low unit costs.

Some designs are less sensitive to unit cost and require lower initial expenditure. For the digital functions, this can often take the form of standard functions in the circuit, such as commercial DSP chips, and even PLDs, or FPGAs. The economics of the latter devices have shown dramatic changes in recent years, and in cases where complex logic functions are needed, even up to 100k unit/year, FPGAs provide a convenient solution, either in the long term or as an intermediate stage before a full custom chip is designed.

Analogue circuits are more difficult to standardise, since they tend to be more function specific. However, many analogue standard functions are available, and to some extent new designs must compete with these for market share.

This module will compare and contrast the capabilities of current and possible future process for use in RF communications and the related areas of optical fibre communications and sensor interfaces.

Note that:

• RF Technology integration is still at an early phase.
• Discrete components are cheap competition to integrated devices.
• The problem with integration is in passive components such as capacitors and inductors.
• Capacitors use a lot of chip area, but are of high quality.
• Inductors use a lot of chip area, and may be poor quality, i.e. low Q.

[back to top]

2.1.1 Passive Components

In any radio circuit, the passive devices such as tuned circuits may be as important as the active devices. Also, aspects such as the replacement of potentially large area passives by small area actives should be at the forefront of the designer's mind.

2.1.2 Thermal Design

Also vitally important in the design process is the thermal design of the chips. Thermal design has in the past been much neglected, in part because silicon is such a surprisingly good thermal conductor for its place in the periodic table. This meant that the chip could be assumed to be isothermal, and the only thermal management issues were those of heat dissipation of the chip as a whole. The advent of silicon-on-insulator (SOI) structures has changed this, since such structures may operate with each transistor effectively thermally isolated from its companions.

The finite element analysis techniques used to examine this issue can be retrospectively applied to conventional silicon, with the result that existing designs are shown to exhibit some thermal errors, most notably in precision circuits such as bandgaps.

GaAs has thermal properties worse than silicon, and therefore needs careful design, but is better than silicon on insulator.

[back to top]

2.2 Main Technologies available for design

The main technologies available to the IC designer are Silicon, in bipolar, CMOS or BiCMOS forms, and Gallium Arsenide (GaAs) primarily in the form of depletion mode FETs, but also available as enhancement FETs, usually in an enhancement/depletion process, and as heterojunction bipolar transistors. More recently, silicon bipolar devices have been produced with the addition in critical areas of Germanium, in the SiGe processes. This again is a heterostructure, with the advantages that gives, but is inherently different from the GaAs heterostructure. Variations on these themes include, in silicon, the use of silicon-on-insulator (SOI) processes. In this case a layer of oxide is introduced below the active devices. This gives lower parasitic capacitances to substrate and in some respects moves silicon operating speeds up, typically to those of the next most advanced process geometry. Also, SOI packing densities can be greater, leading to smaller, faster chips on a given process. There are, however, penalties in process complexity which can compromise yield. CMOS SOI is relatively straightforward, with implantation of the oxygen in processes such as 'SIMOX'. Bipolar devices require lower defect states in the bulk of the material, so 'BESOI' techniques are employed.

Likewise, SiGe can be realised in several different ways, either based on a bipolar process or a BiCMOS process. The former may lead to the best devices in terms of speed; but the latter has better economics in its favour, with the possibility of SiGe, Si bipolar and CMOS on a single chip.

[back to top]

2.2.1 Application Areas

Application for RF based analogue and digital 'radio' chips also include sensor and fibre-optic areas. These will be dealt with in other chapters of this module.

2.2.2 Discrete Transistors

Discretes are still widely used, even in low power RF stages. This is because they are high performance and cost effective. Circuit changes are easily and cheaply made. The presence of bulky components such as inductors means that there is little advantage in integration. Monolithic circuit design at low frequencies is therefore a challenging subject.

[back to top]

2.3 Discrete vs. Integrated Transistors for RF

The table above compares discrete transistors with IC processes against a number of parameters.

From the circuit design aspect, the process minimum dimension is only important in its influence on other characteristics such as speed of operation and noise figure. However, to some extent it does influence costs. More recent processes are usually more expensive; but where this is a cost per unit area, the cost per function is often reducing.

Noise figure is quoted above in an RF amplifier; CMOS is constantly improving, while the other figures are rather static. However, as noted above, in many cases, noise figure should be adequate for the design. There is little point in going beyond that which is needed, especially as it usually involves increases in current consumption.

The comparison above illustrates that discrete transistors still have a place, especially where space is not so important, but where cost and design turnaround time are vital. In a practical radio, the front-end selectivity, usually provided off-chip, may be relatively bulky, as it consists of transformers, inductors and in some cases large value capacitors. Hence the size penalty of discrete devices may not be important.

[back to top]

2.4 Silicon Integrated Circuits in RF

Conventional silicon bipolar devices have had a dominant position in integrated RF design for many years. In contrast, discrete receiver front ends often contain 'dual gate' MOSFETs, invariably N-Channel. As monolithic processes go below 1 micron in critical dimensions, MOS has become more attractive as an RF technology. Approximately, 1 micron devices are useful as RF amplifiers to 0.5 GHz, 0.5 micron to 1 GHz, and 0.25 micron beyond that. Potentially, lower noise amplifiers may be made in MOSFET active devices, since the gate resistances are very low compared with a bipolar device, while source/drain resistances are similar to those of the bipolar emitter/collector. Thus, the total noise resistance may well favour the MOS device, given careful layout. It should be noted that most MOS processes and standard layouts are oriented towards digital circuits and are therefore not optimised for analogue. Also, MOS suffers from a high 1/f corner threshold. This implies that, while RF amplifiers may work well in MOS, mixers will probably be noisier.

Internet keywords

Use the following to search the www:Integrated circuit, analog, (use the US spelling), Radio, Radio Frequency, RF, silicon, CMOS, BiCMOS, Bipolar, silicon, germanium (use combinations of these, e.g. silicon alone will get millions of responses!)

[back to top]

2.4.1 Reverse base-emitter junction

Figure 1 The Bipolar Transistor Cross-section, SOI

Note: This is very diagrammatic, all edges are likely to be less well defined.

A cross section of a bipolar device is shown above. (Mitel Semiconductor). In this instance it is an SOI device, although with the omission of the oxide layer the diagram would map onto many bipolar processes. Vertical isolation of the device is through the oxide interlayer; if this is not present, then the reverse biased junction provides isolation at the cost of greater capacitance. Lateral isolation in this instance is through oxide filled trenches cut into the silicon; again this could be merely reverse biased junctions, with greater capacitance but simpler processing.

WWW Research

Look for transistor structures on manufacturer's web sites. Some are particularly good with information, e.g. IBM and Orbit (now Supertex). Look also for Mosis, which has layout information freely available.

Mosis is a US based, low cost prototyping and small-volume production service for VLSI circuit development. Since 1981, MOSIS has fabricated more than 40,000 integrated circuit designs for commercial firms, government agencies and universities. MOSIS provides designers with a single interface to the constantly changing technologies of the semiconductor industry. Mask generation, wafer fabrication, and device packaging are contracted to leading industry vendors. A European equivalent of Mosis is 'Europractice'. Low cost access is available to many processes on a multi-project wafer basis. Design details usually require signature of non-disclosure agreements, but arrangements are easily made. Recently, Europractice has also made available some forms of micro-machining and other post-process techniques, for innovative devices.

It should be noted that the real transistor action takes place largely in the small volume of base region immediately below the emitter. All the rest is there for isolation and connection. Typically, the base width (i.e. the vertical dimension between emitter and collector regions) in this region is less than 0.2 microns. Base widths narrower than 0.1 micron are possible, at a cost in reduced breakdown voltage. Process design is thus at least a three dimensional compromise of transition frequency (FT) base resistance and breakdown voltage. Clearly as FETs approach (and exceed) minimum dimensions of 0.2 microns, their performance will become comparable with that of bipolars. Concomitantly, the performance compromises will also limitate those of the bipolar devices.

[back to top]

2.5 Transistor Cross Sections - Comparisons

Some simulation packages offer the opportunity to look at the idealised cross-sections of the transistors, through a line chosen by the user. The screen captures below show this for MOS and bipolar devices. These should be compared with the drawings and cross-sectional photographs in this section. In each of the screen shots, the lower section is the cross-section, aligned with the top layout above. Not all through contacts are evident.

Figure 2 Layout and idealised cross section - MOS transistor

 

Figure 3 Layout and idealised cross section - bipolar transistor

Figure 3 0.25 Micron Silicon CMOS Cross Section

Source: IBM

Although most circuits use aluminium metallisation, gold has been used in some critical circuits for many years. Historically, gold was used to reduce carrier lifetimes and thus avoid saturation delay problems in silicon bipolar circuits, However, alternative active devices and better circuit techniques overcame that problem, so gold is conventionally avoided as a 'lifetime killer' and yield hazard. However, used properly, it has many advantages over aluminium, notably better conductivity and better thermal properties under high current conditions. The photo above shows gold metallisation in three layers on a CMOS circuit, with tungsten plugs for layer interconnect, and to keep the gold isolated from the silicon.

Figure 4 Trench Isolated Bipolar Cross Section

Source: IBM

Trench isolation is accepted standard practice in most bipolar processes. It has advantages in CMOS, but is often seen as a yield problem, primarily because CMOS chips tend to be much larger. Nevertheless, it is used, especially in memory devices. A single transistor is shown above. Note as before how small the active circuit is when compared with all the volume required to connect to it. This cross section is actually a silicon germanium transistor as described below.

[back to top]

2.6 Silicon-Germanium

See IBM's web site for more information

Figure 4 SiGe HBT Emitter Area = 0.5 µm x 2.5 µm

Source: IBM

Gain of the SiGe device holds up well down to very low currents. Some gain compression occurs at the highest current densities, as the convergence of the Ic and Ib lines shows, but usually SiGe runs at about twice the current density of the equivalent silicon device. Not shown is the big improvement in base resistance, which leads to much lower noise devices in SiGe. Since the 1/f corner is similar to silicon, the mixer noise in SiGe is also low.

 

Figure 4 SiGe HBT Emitter Area = 0.5 µm x 2.5 µm

Source: IBM

This plot of Ft and Fmax for SiGe shows potentially how fast the devices are. Digital circuits to 25 GHz have been reported, with analogue circuits to over 10GHz.

[back to top]

2.7 Gallium Arsenide

It was found in the very early days of GaAs that bipolar devices were impractical in the basic material itself, primarily due to the short lifetimes of the carriers. Although that problem is now less pronounced, the industry grew up around the MESFET device, which could be produced with relatively high yields.

Recently, heterojunction bipolar transistors have been fabricated in GaAs technologies. The heterostructure may be made in any of several different methods. Essentially, the work is 'bandgap engineering' to define a high mobility region in the semiconductor. The circuits tend to be similar to their silicon counterparts, but with the added advantages of faster devices and minimal parasitic capacitance to substrate.

Sequence of Masks

Source: Marconi Materials Technology

Most Gallium Arsenide work is based around the MESFET. A foundry sequence of masks for the process is shown above. Compared with a silicon bipolar process, GaAs has fewer critical layers, although generally more than a CMOS process

Examples of Inductors on a chip

Source: Marconi Materials Technology

Where GaAs notably wins over silicon is in the use of on-chip inductors. As noted below, these have better Q characteristics than is possible on a silicon substrate. The chip above illustrates this point, with a multi-stage, inductively matched structure. Running from left to right, there is a twin inductor/capacitor input matching arrangement feeding two small FETs. From there, a two-stage matching/filtering circuit takes the signal to three larger devices, again with inductive loads and bias isolation. This is a power amplifier for the low-GHz bands. Many such devices are available from a small range of manufacturers with particular skills in this area.

[back to top]

2.8 Inductors and Transmission Lines

Three layers of metallisation

All modern processes offer two, and usually more, layers of metallisation. These are usually seen as interconnection, but are equally useful in the RF context as parallel plates for capacitors and as inductors or transformers. Monolithic inductors take up significant chip area, and are usually avoided, although newer thinking on this topic is less dogmatic than, say, ten years ago. There are two fundamental loss mechanisms in the inductor. The first is just loss in the conductor material. Although aluminium has low series resistance, the very narrow conductors used result in resistances of ohms or tens of ohms. This is usually unacceptable in Q terms. Wider tracks may be used, but this increases parasitic capacitance to substrate, thus loading the inductor and therefore reducing its maximum operating frequency.

Resistivity of silicon and gallium arsenide

The second loss mechanism is in the lossy substrate material. The relative positions of silicon and GaAs are shown in the resistivity plot above. Typically, GaAs is in the 'Dielectric Quasi-TEM' mode, i.e. the substrate acts as a waveguide. Silicon, with lower resistivity, also tends to operate at lower frequencies, in the 'Slow wave' mode. The resistivity of silicon as used in IC manufacture is such that losses occur; it is roughly at the peak of the loss resistivity. The reasons for this relate to Maxwell's equations. Consider a perfectly conducting substrate. Then, ignoring any effects on active devices, the inductor would see only the dielectric layer, probably silicon dioxide, between it and the perfect conductor. Although the impedance level, due to the high capacitance, would be low, the loss would also be low, as the loss mechanism would be limited to that of the series resistance.

The alternative case is that for a perfect insulator substrate. In this case the inductor would be further away from the perfect conductor, i.e. the back wall of the substrate, typically mounted onto a conductive header, but again the loss mechanism in the substrate would be negligible. Between these two states lie all practical semiconductors, i.e. there is always some substrate conduction and hence some loss. In GaAs, described as a 'semi-insulator' in its highest resistivity state, losses are usually very low. In silicon however, losses are significant.

Typically, the substrate loss term is designed to roughly equal the conductor loss, since there is little point in one being very much better than the other. Silicon on insulator, SOI does give some advantage, since it inserts a loss-free layer. However, the same effect can be achieved using a thicker oxide on the top of the wafer, at greatly reduced cost in processing. Typically, Silicon inductors have Q values of 2 - 5 at 2GHz. SOI can achieve 6-11, while GaAs may exceed 20. One major advantage of on-chip inductors is their low cost and great reproducibility. In the right design, they are useful and cost effective.

[back to top]

Transmission Lines

On silicon, transmission lines tend to be lossy for the reasons noted above for inductors. SOI is an improvement, and GaAs substrates are better again, although a costly means of producing transmission lines in themselves.

Characteristic Impedence of transmission line vs ratio W/H for materials with various relative permitivity

The key parameter for transmission lines is their characteristic impedance. Conventional RF circuitry now uses the 50 ohm standard virtually universally. This may be achieved on chip with relative ease, but it does lead to narrow tracks with their consequent losses. There is no particular need to stick to 50 ohms, or indeed any other specific level of impedance. There are many attractions in using very wide tracks on silicon, and hence achieving low resistances. The low impedance also implied by the wide track is also beneficial in power terms, since all IC processes are inherently limited to low voltage operation. Thus low impedance, correctly managed, may lead to low voltage, high current and hence (relatively) high power operation. This is of course primarily of use in the transmit path. In receive, low power operation is desirable and hence impedances may be higher.

[back to top]

2.9 Stripline Filters

Stripline filters are widely used in GaAs, where losses are acceptable, but very little used in silicon, where losses are high. Also, since stripline filters are fundamentally linked in dimensions to the wavelength in use, they become impractical at frequencies much below 8GHz, again favouring the GaAs technology. It may be that SiGe circuits take advantage of stripline elements, but this has not been evident to date.

[back to top]

2.10 Package Effects

Packaging is critical to all RF components, in any technology. The 'system on a chip' approach has the attraction of minimising external packaging effects, while many current RF ICs suffer from too many connections to the outside world, typically to inductors and filters which are necessarily off-chip. This is shown above in the comparison with discrete components. At low frequencies in particular, there may be little advantage in higher levels of integration due to the interconnect parasitics.

GaAs IC designers have long been familiar with packages designed around 50 ohm impedance lines; this is now becoming more applicable to silicon RF ICs.

[back to top]

2.11 Thermal Issues

Silicon on insulator is non-iso-thermal at mA currents, ie. the device self-heats. This can be problematic in circuit design, but can lead to novel devices. The simplest design approach is to operate at currents below that which causes significant self-heating, but this negates many of the advantages of SOI processes, especially where speed of operation depends on high Ft and therefore relatively high currents.

Thermal problems in SOI

The simulation above is for a small transistor dissipating 5mW in an SOI wafer. The centre of the device rises by 13 degrees, while the surrounding region outside the thermal tub formed by the transistor sidewalls and the SOI layer is not substantially affected. Higher dissipation devices, for example in SiGe, may be over 100 degrees above the background. Substantially all the thermal gradient occurs in the oxide isolation. Thus circuits which depend on iso-thermal conditions, such as 'bandgap' references, are likely to be non-functional.

[back to top]

2.12 Digital Circuitry Requirements

Digital circuitry is required in the RF environment in several areas:

• Frequency Synthesisers
• Digital signal processing of received signals
• Digital signal processing of transmitted signals
• Intermediate frequency processing
• Demodulation and modulation
• Control functions

These requirements are varied in their frequencies and integration levels.

In addition to the RF and digital performance, real 'System on a chip' products need low speed digital circuitry, capable analogue circuitry and probably analogue to digital and digital to analogue converters. In all these areas, CMOS is supreme, and all other processes should be compared with it.

Summary: The ultimate process should be CMOS, but bipolars are desirable, thus pushing towards BiCMOS. If really fast digital circuits, with broadband analogue circuits, are needed, then SiGe BiCMOS is the main contender. Finally, if excellent device to device isolation is required, then SOI techniques should be used. Such a process is probably no more than two years away. GaAs is the process of choice for RFonly applications. Its limited capability in other areas may sometimes be a problem, but the operating frequencies of RF circuits are likely to stay ahead of silicon based alternatives, and the semi-insulating substrate is a major advantage.

[back to top]

Site Search

Powered by Google
Site Map