Communications IC Architectures
Unit 3a - High Speed Digital Design for Communications Circuits
This chapter describes the digital support circuits which are invariably needed for communications. Any communications system should be integrated into a very few separate chips; ideally just one. Therefore, as the chapter on Process Choice has shown, it is important to make the choice of process as near optimal as possible. High speed bipolar logic remains an important technique for frequencies above 1 GHz, up to say 10GHz, although Silicon-Germanium extends this to at least 25GHz. Although Gallium Arsenide has attractions for RF circuits, its logic capability is more limited (see chapter 3b).
Unit Contents
- 3.1 Background
- 3.2 Circuit Simulations
- 3.3 Applications of High Speed Logic in Communications
- 3.4 Limitations to ECL
- 3.5 Summary
- 3.6 Web References
3.1 Background
Background Silicon bipolar ICs were the first viable form of logic. The earliest
versions were resistor-transistor logic (RTL), diode transistor logic (DTL)
and eventually transistor-transistor logic (TTL). TTL came to dominate the field,
with variants such as Schottky TTL, low power TTL and low power Schottky TTL.
All these families are now essentially obsolete; silicon CMOS has taken over
in all speed ranges covered by these techniques.
High Speed Bipolar Logic
From the earliest days there was an alternative to TTL, called emitter coupled logic, ECL. ECL was, and remains, the fastest logic family. Conventional, i.e. "discrete" type ECL is power hungry but internal versions can be very efficien
| Family Series | TTL | ECL | CMOS* |
|---|---|---|---|
| Parameter | 74LS 74AS 74ALS | IOK IOOK | 74C 74HC |
| Nominal Supply Voltage, V | 5.00 5.00 5.00 | -5.20 -4.50 | 5.00 5.00 |
| Maximum VOL, V | 0.50 0.50 0.50 | -1.70 -1.70 | 0.40 0.40 |
| Minimum VOH V | 2.70 2.70 2.70 | -0.90 -0.90 | 4.20 4.20 |
| Maximum VIL V | 0.80 0.80 0.80 | -1.40 -1.40 | 1.00 1.00 |
| Minimum VIH V | 2.00 2.00 2.00 | -1.20 -1.20 | 3.50 3.50 |
| NMH, V | 0.70 0.70 0.70 | 0.30 0.30 | 0.70 0.70 |
| NML, V | 0.30 0.30 0.30 | 0.30 0.30 | 0.60 0.60 |
| Logic Swing, V | 2.00 2.00 2.00 | 0.80 0.80 | 3.80 3.80 |
| Power Dissipation per gate, mW | 2.00 20.00 1.00 | 24.00 24.00 | 0.00 0.00 |
| Delay, ns | 1.00 1.50 4.00 | 2.00 0.75 | 30.00 10.00 |
| Fan-out | 100 10 100 | 10 10 | 100 100 |
| * Measured at a load current IOL 4mA. At IOL = 0.2, VOL = 0.1V and VOH = 4.8V. | |||
The table above compares the TTL families with ECL and CMOS. Note that the
static power dissipation of CMOS is zero, i.e. an unclocked gate draws no power
at all. This contrasts with TTL and ECL, which in 'discrete' logic form use
significant power when unclocked. In LSI/VLSI form, ECL can actually be more
power efficient than CMOS at high clock rates, but this static advantage for
CMOS is very important.
SAQ
PCompare ECL and CMOS logic on a VLSI basis, using 'internal' gate delay figures, based on data sheets for foundry services.
Web search terms:
LVLSI, CMOS, ECL, gate delay, 'silicon foundry'
Foundry suppliers:
AMS (Austria Mikro Systeme, vertical-global.com), TSMC, Orbit
Semiconductor.)
ECL 3-Input Gate
Internal ECL gate. Operates from any supply 2.0V to 5.2, bias permitting
The circuit above is a basic internal ECL gate. Multiple inputs are easily added, and the supply voltage may be very low, as low as 2 volts, provided that the voltage swing is also low.
Self-Referenced ECL
N.B. Has positive feedback so operates with a Schmitt trigger action.
3 Input Full ECL Gate
Bias levels are critical to achieving correct temperature coefficient. This
varies between the families, which are:
ECLIII obsolete
ECL10K obsolete
ECL 100K Fastest
ECL10KH Fast
Only the last two of these are fully temperature compensated
Level Stacked Logic
Complex logic functions may be achieved, minimising through delay
Typically internal to an ECL chip, the logic is stacked for greater efficiency and speed. Fairly complex functions may be obtained with minimal use of current, and importantly the function can be realised with the minimum delay.
Multi-level ECL
Q=(A+B).C.D
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3.2 Circuit Simulations
3.2.1 Self-Referenced Logic
Self-Referenced Logic simulation
Note first the hysteresis involved in the logic gate
Self-Referenced Logic simulation
The logic threshold shown above is 225mV, with a sharp transition.
Self referenced logic - simulation with triangle input
Transition remains fast with overshoots. Negative threshold 228mV; positive threshold 110mV
3.2.2 Emitter Coupled Logic
Long tailed pair, as in ECL core gate
The ECL core gate shown above requires the use of two voltage references, respectively for the current source at the bottom and for the logic reference. Note that the gate closely resembles a long-tailed pair amplifier, which is just what it is. As for an amplifier, transistor gain is important, as is output impedance. A minimum gain of beta=40x is essential for ECL, with an Early voltage of over 30V.
Simulation with triangle input
Unlike self-referenced logic, the transition has no hysteresis. Because the circuit has gain, there is some speed up of the output, but not much. The output is symmetrical in voltage and time. A full ECL logic swing is over 800mV, but internal gates often operate down to as low as 200mV. As shown here, the emitter followers are also often omitted, although the very fastest circuits do use followers, sometimes duplicated.
Full ECL configuration with single followers
The above circuit is a full ECL configuration with single followers. This is similar to that of 'discrete' ECL gates, and to the inputs and outputs of VLSI devices.
ECL circuit - simulation with triangle input
ECL circuit at 50 MHz
ECL circuit at 50 MHz
3.3 Applications of High Speed Logic in Communications
The two main areas for high speed logic in communications are in frequency synthesisers and in data multiplexers/demultiplexers for digital transmissions. The requirements for both areas are similar, with operation to several GHz desirable. Synthesisers for mobile equipment in particular need to be low power consumption.
The combination of high speed logic circuits and low 1/f noise oscillators in the synthesisers and low noise amplifiers for the front end give bipolar many attractions for use in radio circuits. Up to say 2 GHz, it is possible to build efficient, low power radios in a single chip approach. SiGe can extend this to at least 5GHz, possibly 10GHz.
3.4 Limitations to ECL
3.5 Summary
SAQ
Using data obtained above, simulate a chain of 4 D-type dividers. Use most power in the first stage, for fastest speed of operation, then reduce power to successive stages.
What simulated speed can you achieve?
What are the practical problems in doing this?
3.6 Web Refrences
Terms: 'emitter coupled logic', silicon vendors.
Try also National Semiconductor, Philips, Siemens, Mitel.
Look especially at research sites, e.g. University of Bochum (Germany).