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Communications IC Architectures

Unit 3b: Gallium Arsenide High Speed Logic 

Prerequisites for this chapter Chapter 2, Process Choice for Communications

Unit Contents

• 3.1 Introduction
• 3.2 Logic Families
  • 3.2.1 Depletion Mode Logic
  • 3.2.2 BFL Gate Design Issues 
• 3.3 Circuit Simulation
• 3.4 Optimisation of Design
• 3.4.1 Device Geometry
• 3.4.2 Speed and Statistics
• 3.5 Commercially Available Digital Processes
• 3.5.1 TriQuint Foundry Fabrication Processes
• 3.6 Summary
• 3.6.1 Acknowledgement
• 3.7 Self Assessment
• 3.8 Internet keywords

3.1 Introduction

Introduction This chapter will describe high-speed logic using Gallium Arsenide technology. Although not as commercially important as silicon bipolar logic, and certainly much less so than CMOS, GaAs has found a niche, primarily as support circuits for microwave analogue/RF circuitry. In many applications, monolithic implementation is vitally important, so the addition of GaAs logic to a microwave chip can be a strongly enabling technology. A typical example is in a microwave 'front-end' where a prescaler for the synthesiser is needed. Silicon, possibly in SiGe form, could probably do the division, but GaAs is needed for the low noise RF circuits. A system consisting of a GaAs RF circuit and prescaler will enable the rest of the circuit to be realised on a low frequency CMOS IC.

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3.2 Logic Families

The logic families are:

• Depletion Mode Logic

- Buffered FET logic, BFL

- Source Coupled FET Logic SCFL
 
 

• Enhancement-Depletion Mode Logic

- Source Follower Direct Coupled FET Logic SDCFL

- Source Follower FET Logic SFFL The relative merits of depletion when compared with enhancement/depletion mode are:
 

• Depletion Mode

- Poor packing density, since gates need many component parts (see below)

- Two power supplies ( also see below)

- High power dissipation (relatively)

- High speed
 

• E/D Mode

- Poor fanout

- Good packing density

- One power supply

- Medium/low power dissipation

- Moderate speed Why is enhancement mode a yield hazard?

The problem is noise margin. Unlike MOSFETs, the input of a MESFET is a junction diode. Under some bias conditions it will conduct, i.e. go into forward bias. Thus the threshold of the enhancement device should be above zero volts, but below the threshold of conduction, typically at 0.7 volts or less. In process control terms, this can be difficult to achieve on a worst-case basis for large numbers of devices. In the past, this has limited the application of such devices to small-scale circuits where low yield was not an issue. However, more recently, process control has enabled VLSI complexities to be achieved. Accurate process control is vital.

3.2.1 Depletion Mode Logic

• BFL is oldest, fastest GaAs logic format
• BFL needs diode based level shift (see below)
• Schottky Diode FET Logic, SDFL, has speed problems, and no real advantages
• Other forms of level shift such as capacitor-coupled logic do not really work for LSI/VLSI

Fig 1 :Simple BFL Gate - 2 Input NAND

The above shows a simple BFL gate, a 2-input NAND. The complexity when compared, say, with a CMOS gate is evident. What is less evident is that the voltage swing is small and difficult to manage with realistic component tolerances. However, until very recently, this was the fastest logic gate available in any mainstream technology. SiGe may be faster in the latest variants, but the difference is not great. The circuit needs two power supply voltages for operation The level shift, which is essential to make each stage drive into the next, is complex and must be correctly toleranced for consistent operation.

Fig 2 : BFL Simulation at 1GHz

This shows a simulation of this logic gate at 1GHz, clearly not a limiting condition. Note however that the voltage swing is low, 1V, when compared with the supply voltage, and especially so when compared with the level shift voltage and the potential variation of the level shift with process variation.

Fig 3 :Complex BFL Gate

Two 2-input NANDs feeding a 2 input NOR

There are some advantages in moving to a more complex logic gate, since the function achieved in so doing may be more versatile. Combined gates such as the above are very frequently employed in GaAs technology. Broadly similar techniques will also be seen in silicon bipolar, although less so in CMOS. In the example shown, only a single level shift is needed, although the total function of the gate includes two NAND and one NOR gates.

Fig 4 : Complex Gate Simulation at 1GHz

The simulation of the more complex gate is shown above. Clearly operation at 1GHz is not difficult, and much more is possible.

3.2.2 BFL Gate Design Issues

• Two power supplies are needed
• A complex (in component count) level shift is needed
• The voltages of the supplies, the threshold voltage of the process and the level shift must be closely linked and controlled
• When designed well, gate performs well
• Significant optimisation needed, but only once for a repeatable process
  
  

Fig 5 :BFL Gate at 5GHz - just beyond reasonable operation

The simulation above shows operation at around the limit for the device parameters used. Faster processes push this limit to over 10GHz, although relatively little development is in progress for digital GaAs circui0ts.

Fig 6 :Enhancement Logic - DCFL

An enhancement GaAs logic gate is shown above. This circuit is much simpler than BFL and is similar to the circuits used in NMOS, the predecessor to CMOS. However, the forward conduction region of the transistors should be avoided, so the voltage swing is limited.

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3.3 Circuit Simulation

Fig 7 : DCFL Simulation

enhancement device characteristics are the same as for depletion; there is just threshold shift

The simulation above is for direct coupled FET logic, DCF, ie. enhancement/depletion mode circuitry. Note the small voltage swing and the low output voltage. What advantages and disadvantages does this convey?

Fig 8 : Three Stage DCFL

simple circuit. E = Enhancement Device

The extension to multiple stages is obvious and more complex gates may be arranged, but the lack of supply voltage 'headroom' limits the stacking of logic stages above each other. Such stacking is possible in principle, but tends to negate the advantages of simplicity.

Fig 9 : Three Stage Simulation

enhancement device characteristics not quite optimised. The shift of levels can be corrected

The simulation of the above circuit shows some problems; the average DC level is shifted up. Further optimisation of levels would be needed in this circuit.

Fig 10 : SDCFL Circuit, two stages

Just two inverters here; a relatively complex circuit.

A variant on the E/D circuit is SDFCL, where additional buffer stages are added. This is attractive in easing the matching and threshold control requirements, at the cost of a more complex circuit with greater gate delay.

Fig 11 : SDCFL Simulation

more stage gain - at the cost of added complexity

SDFCL is capable of high-speed operation, but this is best seen where there is no feedback loop, i.e. not in a divider.

Fig 12 : SDFCL Wired-OR

More complex functions are easily achieved in SDFCL using, for example, the 'wired-OR' structures.

Fig 13 : SFFL Connection

Alternative structures really amount to alternative connections in some cases, as above. Various authors describe the advantages and disadvantages of the structures.

Fig 14 : SFFL Simulation - better drive capability

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3.4 Optimisation of Design

• The process variables are:

• It is necessary to optimise:
  
  - speed
  - 'DC' characteristics
  - yield

  Threshold Voltage - the design criteria
 

•  The input threshold voltage is critical for DCFL

- must be higher than Max V_OL of previous stage
 

• Noise margin L = V_t - Max V_OL

- Must be lower than Min V_OH of previous stage
 

• Noise Margin H = Min V_OH - V_t
• And for the Level Shift (BFL variants):

• The level shift wastes power

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3.4.1 Device Geometry

FET devices are characterised, in part by their mutual conductance, 'gm'. This is a measure of the change in output current caused by a change in input voltage. Hence, the factor is conductance, and the term 'mutual conductance' is used.

In addition, all FETs have parasitic capacitances. Since the device size is closely linked to the capacitance and to the gm, these are not independent factors. The gm/C ratio of FET devices is fixed by the process, except very small devices which tend to be worse. To minimise power consumption and chip area, small devices should be used. Logic gate optimisation requires control of currents, supply voltages and minimisation of parasitic capacitances. Logic gate speed is determined by the total capacitance, load and parasitic, and the driving point output impedance, which is typically 1/gm. Hence, gm/C ratio is an excellent figure of merit for a digital process.

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3.4.2 Speed and Statistics

• Speed is also affected by variations in supply, Vt, and by process variable capacitance.
• It is possible to calculate speed variation with process.
• Vitesse process limited by this calculation to 500MHz, although this is probably pessimistic.
• Best figures suggest 10k gates are possible (on Vitesse process) using BFL.

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3.5 Commercially Available Digital Processes

• Vitesse Semiconductor

• Triquint Semiconductor

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3.5.1 TriQuint Foundry Processes

• TQTRX is 0.6 micron, E/D, three layer metal for interconnect - best choice for digital and mixed mode.
• HA2 is 0.5 micron depletion only - really an RF process.

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3.6 Summary

• GaAs MESFET logic is available.
• For mainly RF chips, some logic in BFL may be acceptable, say for prescalers etc. where speed and 'one chip' approach useful.
• DCFL and variants are mainstream 'GaAs digital', but speeds poor;  c.f. silicon bipolar, even CMOS catching up.
• 'Area' problems of BFL can be overstated, especially where a large RF chip needs a few digital functions; can be put 'into a corner'.
• Power is also less of a problem for the simple functions.

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3.6.1 Acknowledgement

Some simulations in this chapter have been carried out using data supplied by Marconi Technology, Caswell.

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