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Communications IC Architecture

Communications IC Architectures

Unit 4: Phase Locked Loop Frequency Synthesisers

Introductory text....

Unit Contents

4.1 Phase Locked Loop Frequency Synthesisers

PLLs have been in use in practical systems for about 50 years. The function of a PLL is to lock a frequency wanted in the system to an accurate reference frequency. Desirable characteristics of the reference are time and temperature invariance, and low noise. These topics will be described below.

 

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4.2 Terminology

No oscillator gives an absolutely pure output signal. In particular, oscillators which are generated by synthesis techniques are prone to additional outputs and noise when compared with a free-running oscillator; but the latter lacks the stability needed for communications systems.

Fig 1 :Typical Oscillator Output

Typical Oscillator Output

In the diagram above, the situation is much simplified. One signal is labelled as the 'wanted output'. Ideally, this would be the only output from the oscillator system. However, more typically, it will have noise sidebands, it will often have harmonics present, and it will sometimes exhibit non-harmonic spurious output frequencies. Each of these also will show noise sidebands, so the whole spectrum can rapidly become confused.

 

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4.3 Analogue Synthesisers

Analogue synthesisers have been available since at least 1945, and they remain in use in certain applications. All PLLs are really a combination of analogue and digital techniques, and even some modern PLLs have a high analogue content, especially for low noise on a limited range of microwave frequencies.

Fig 2 :Simple analogue synthesisers

Simple analogue synthesisers

A simple analogue synthesiser is shown diagrammatically above. The source of stability in this case is two banks of precision quartz crystals. One crystal from each bank is switched into an oscillator circuit, and the results of the two oscillators are mixed together and then filtered. Band pass filtering is usually necessary to ensure that other harmonics and mixing products from the two oscillators do not enter the output port.

This synthesiser, if well built mechanically, can achieve very low noise levels, and good stability, because:

1) Crystal oscillators are very low noise.
2) The stability is achieved at frequencies comparable with that of the output, ie there is no division and multiplication.
3) The circuit can avoid digital 'glitches'.

Against these benefits must be set the disadvantages of the cost of the many crystals, and the relatively small number of discrete frequencies available. Crystals are also subject to ageing and mechanically induced noise.

Fig 3 : Multi - output analogue / digital synthesisers

Multi - output analogue / digital synthesisers

A block diagram of a recent multi-output analogue/digital synthesiser is shown above. In this approach, a harmonic generator produces many harmonics from a 1MHz source. These are then selectively filtered and in some outputs divided by a digital circuit. Multipliers are also added for some outputs, and clearly further mixing and filtering would also be possible. However, the cost of building and aligning such a complex system, especially the selective amplifiers, would be high. In this case, those costs were considered to be offset by the benefits of multiple outputs with a single reference, ie all outputs would be nominally in phase.

 

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4.4 Digital Phase Locked Loop Synthesisers

Fig 4 : Digital Phase Locked Loop Synthesisers

MuDigital Phase Locked Loop Synthesisers

A more practical system is outlined in simplest form above. This diagram shows what is conventionally known as a 'digital phase locked loop synthesiser' although clearly the VCO and loop filter are analogue parts, while the phase detector could be analogue or digital or a combination of both. The VCO is set approximately on the wanted output frequency. That frequency is divided down to a lower reference frequency by a variable ratio divider. For example, if the reference frequency was 25kHz, and the divider ranged from 80 to 100, the output frequency would be variable between 80 x 25kHz = 2 MHz and 100 x 25kHz=2.5MHz. This assumes that the VCO is tuneable over the range, and that the control voltage will cover an appropriate range for the VCO. Details of this are indicated below.

Unfortunately, it is a fact that fully variable ratio dividers such as the above are limited in upper operating frequency range, typically to a few MHz.

Fig 5 : Fixed ratio divider added to digital PLL synthesiser

Fixed

Adding a fast fixed ratio divider ahead of the variable divider above could make a faster synthesiser. However, in relation to the output, this uses a lower reference frequency, which may be considered undesirable.

 

Fig 6 : Narrow range digital PLL frequency synthesiser achieved using a mixer

Narrow

An alternative scheme, which has many attractions, is shown above. In this case, the VCO frequency is mixed down to the range where the programmable divider is operative. The mixing uses an offset crystal frequency, typically at >100MHz. The useful range of this synthesiser is very limited, but narrow channel spacing is possible without recourse to impractically small comparison frequencies. A typical application for this class of synthesiser is in portable and mobile PMR ( private mobile radio) systems such as the police and security 'walkie talkies'. These operate in the VHF and UHF frequency regions. In the diagram above, suppose that the frequency required is 150MHz to say 155MHz. Then if the mixing frequency is 145MHz, the output of the mixer will be 5MHz to 15MHz, which can be handled by a programmable mixer chip. Of course, the VCO range should not include the image frequencies of 145-(5 to 15MHz), ie 130MHz to 140MHz. If it did, there is a possibility of lock-up on an incorrect frequency. This illustrates that wide frequency ranges are not easily achieved in this type of synthesiser.

4.5  Channel Spacing Issues So why not just have a prescaler (fixed modulus divider) ahead of the variable divider? The reason is that the comparison frequency becomes impractically low. As a first estimate, the loop filter roll off frequency should be about 1/10 of the channel spacing to achieve acceptable adjacent channel performance; better may be needed, and this is the reason for the multiple order filters. Consider also some practical numbers. Suppose that the channel spacing is 25kHz - very wide by modern standards. Suppose that a fixed ratio divider of 100x was in use. Then the comparison frequency would be 250Hz. Divide by 10 again for the loop filter, so the loop bandwidth would be 25 Hz. This gives a best case loop lock-up time of 1/25 = 40 milliseconds. Practically, it would be slower than this. This performance is not usually acceptable. Noise sidebands also have impact on these low frequency comparisons.

Without the prescaler, the loop lock up time could be 100x faster, although practical loops rarely better 0.5ms.
 

4.6  Multi-order loops

Channel spacing of a few kHz is usual for FM (Frequency modulation) but some communications, primarily on HF (1MHz - 30MHz) is carried out using single sideband (SSB). At HF and VHF, some communications modes such as frequency shift keying (FSK) also require excellent stability and small frequency increments. In these applications, increments  of 100Hz or better are essential. The section above noted the effect of this on loop response time. One solution to this is to nest several loops together, so that one loop has a fast response, but deals only with coarse increments, while successively smaller increment loops deal with the fine frequency adjustment. Clearly such systems are complex and should be very carefully designed. Systems of four loops deep have been built. Ultimately, however, most of these systems have settling times related to the finest increment. One means of alleviating this problem is to use a variable crystal oscillator (VXO) within the loop. This applies most usually to the frequency offset type of loop, and consists of a digital to analogue converter which drives a varactor tuning the fine frequency of the crystal. While this will only give a very small shift, it may be sufficient to tune on 100Hz increments in a synthesiser designed with true 1kHz steps. It is a technique primarily used in lower cost units, and is not readily adaptable to monolithic integration.

There are several other ways around this, and these will be discussed in a separate module (DDS).

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4.7  Dual and Multi-Modulus Dividers

Fig 7 : Dual Modulas Divider

Dual Modulas Divider

There is a need for very fast 'variable ratio' dividers, and some forty years ago this was solved by the advent of the 'dual modulus' divider.

The inputs to A and M are lower than the input from the VCO by the factor N, or N+1. When the A counter is full, the control signal sets the prescaler to divide by N until the M counter is full. The count is thus:
 

(N+1) x A + N x (M-A)  =  N.M + A

Dual (or even triple) modulus dividers may be made very fast, so the variable modulus advantages may be taken up in frequency to the microwave region. Note, however, that there is some loss of generality; not all ratios are possible. Typically, a large contiguous range of ratios is possible but not the lowest division ratios. This is rarely a problem.

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SAQ

Compare and contrast analogue and digital techniques for frequency synthesisers. What other forms are there in addition to PLLs?

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Internet keywords

Use the following to search the WWW. Search primarily within the sites of major IC manufacturers such as Philips, Texas Instruments, Harris and Analog Devices: Phase locked loop, PLL, synthesiser, phase sensitive detector, programmable divider

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4.8  Noise Multiplication from the Reference

The ideal reference has a low noise level, set by the active devices in use, the frequency, and the loaded Q in operation. Some figures will illustrate this: Assume a 1GHz output, with a 25kHz reference:

1GHz/25kHz  = 40000
or in dB,  40000  = 92dB

This indicates that, at 1GHz, with a 25kHz reference, the noise performance at equal offset from the carrier will be degraded by 92dB. This is a very important concept. Note especially that it refers to exactly the same frequency offset from the carrier, ie. 1kHz at 1GHz is clearly much closer to the carrier than 1kHz at 25kHz. Also, this reference degradation is unavoidable; circuit means may minimise it, and there are additional techniques which may give some improvements at great cost, but the figures noted above are correct for most practical conditions. Practical Reference Notes:

In logic families,
  So, for the reference, dividing down from 10MHz to 25kHz  gives:

10MHz/25kHz=400=52dB improvement over the reference at -150dBC/Hz.

However, the divider will limit to -160dBC/Hz (CMOS, 1kHz)  so the best 25kHz reference is likely to be only -160dBC/Hz at 1kHz, in whatever manner it is realised.

When this is multiplied to 1GHz, the performance is then degraded by 92dB, so the conclusion is that the 1GHz source will have noise sidebands at :
-160dBC + 92dB = - 68dBC/Hz at 1GHz.
 

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4.9 Phase Detection

There are many circuits for phase detection, both analogue and digital. The analogue filter method is attractive in that it is usually the lowest noise technique, and will often give a very uniform 'pull-in'. A mixer with a DC-coupled output is an example of such a circuit and ring mixers of the type commonly used in RF applications have been deployed in this application too. In monolithic form, the 'Gilbert cell' type mixer/multiplier may be used, although is usually needs some form of output level shift and gain. The essential point is that the output is a low frequency, ideally DC, proportional to the phase difference between the signals from the divided VCO and the reference.

The main problem with the analogue phase detector is that it has a limited pull-in range, typically from -p/2 to +p/2. In effect, this means that it will lock to harmonics/subharmonics of the signals, and thus has limited use. Also, its speed of lock-in is usually slow.

One application for analogue phase detectors is as a "close to lock" final detector, typically acting with a digital phase/frequency detector for coarse lock.

Fig 8 : Digital Phase Sensitive Detector

Digital Phase Sensitive Detector

Source: Motorola

A more general-purpose circuit is shown above, first used by Motorola in their bipolar (and later CMOS) phase sensitive detectors. This digital circuit offers both phase and frequency detection, and so does not lock up on harmonics or sub-harmonics. The operation is fairly complex, more so than similar circuits which use two D-types and an inverter/NAND gate. These latter tend not to offer the sub-harmonic lock protection of the Motorola circuit.

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4.10 The Charge Pump

The phase sensitive detector (PSD) circuit shown in the previous section has outputs labelled 'up' and 'down'. The function of these is to drive a circuit known as a charge pump. This circuit shows a simplistic R-C output filter; better filters are often used.

Fig 9 : Charge Pump

Charge Pump

  In the 'up' condition, the inverter puts a low voltage on the gate of M1, turning it on, and thus pulling the junction of the FETs upwards. In the down condition, M2 is on and the junction is pulled down. The logic prevents a dual on condition, while conditions for both devices off occur for much of the time, notably in lock. The R-C circuit filters the response.

Fig 10 : Two frequencies brought into lock

Two frequencies brought into lock

Simulated operation of the circuit is shown above, in this case at low frequencies for clarity. The two upper traces are two VCO frequencies, one used as a reference, with the other pulling into lock with it. After a few milliseconds, the output voltage from the filtered charge pump output stabilises at the appropriate figure. In this instance it is rather underdamped.

Fig 11 : TSignal in lock (in antiphase)

Signal in lock (in antiphase)

The VCO results, digital in this case, are shown above. The signals are in lock, in anti-phase. The phase/anti-phase operation is decided by the exact circuit configuration.  

Fig 12 : Spectrum of the two frequencies

Spectrum of the two frequencies

Spectrally, the two signals are very close. The locked output shows some sidebands, but these are in part due to the FFT, which was taken from the start-up, rather than after lock, so additional frequencies are to be expected.

Fig 13 : Second order filter

Second order filter

 Better loop filters are also a possibility. This diagram shows a second order loop filter.

Fig 13 : Third order filter

Third order filter

A third order loop filter is shown above.

The components are selected to achieve the desired loop bandwidth and damping factor, where:

   

A useful starting  point for D is 0.7. The PLL illustration above has lower damping. Great care is needed in all PLLs to avoid noise on the drive line to the VCO; otherwise, this causes severe modulation of the signal phase. The capacitor types are particularly important. Many ceramic capacitors of high value show random small variations in value. Used at this critical point, this can raise noise floors by 20dB or more above the theoretically expected level.

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4.11 Noise From Active Devices

Noise can come from many sources as noted above.  Critical aspects are the choice of active devices and  the existance of resistance in tracks in signal paths. Where available, FET devices make better oscillators than bipolar devices, since the noise level is usually dictated by the gate series resistance which is lower than the base resistance for comparable bipolar devices. However, compound semiconductor FETs, such as GaAs suffer high 1/f noise, and so are not ideal as

Fig 15 : Relative amplitude of noise around carrier

Relative amplitude of noise around carrier

 

Noise close to carrier can be characterised as above. The noise power in these sidebands is summarised by the equation:
 
 

 

Fig 16 :Simulation of noise components in PLL output

Simulation of noise components in PLL output

For a PLL, it is possible to calculate the noise sidebands of the VCO and of the multiplied up reference within the band of interest. Although this tends to a be a 'best case', ie. the figure which cannot be bettered without radical changes, it is useful in predicting what might be achievable. Such a calculation is shown above and below. Factors in the spreadsheet calculation include device noise, circuit loaded Q, reference noise and frequency and output frequency. The effect of loop bandwidth is seen, especially in the output noise peak, in the second plot. Far away from carrier, the VCO is the dominant noise source, while close in the effect of the loop is to greatly reduce the effective noise, ie. through stabilisation.

Fig 17 :

As an example of current practice, a paper from the recent literature is strongly recommended (Razavi et.al.  IEEE Journal of Solid State Circuits, May 1997).  In this paper, a PLL on a BiCMOS chip operating at 2GHz is described.

The output spectrum is shown below, with a comparison of the free running oscillator and the phase locked version. The effects of the PLL can be seen clearly in the reduction of the noise spectrum.

Fig 18 :2GHz PLL output.

2GHz PLL output.

VCO o/p pack at left, PLL o/p pack at right. Source:  Razavi Characteristics of Razavi's Synthesiser

Centre Frequency   2GHz
Power Dissipation    1.6mW
Tracking Range   100MHz
Capture Range   70MHz
Jitter      2.8ps rms
Phase Noise    -110dBc/Hz at 400kHz
Supply     3Volts
Technology     0.6µm 18GHz BiCMOS

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4.12  Summary

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4.13 SAQ

Compare PLLs with alternative synthesisers such as DDS and fractional-N. This will need extensive data gathering. Prepare you data from web sources/others.

 

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