Communications IC Architectures
Unit 5: Chip Design - Simulation
Unit Contents
- 5.1 Concepts
- 5.2 What Simulators are Available?
- 5.3 Optimisation through Simulation
- 5.3.1 Device Size Sweep
- 5.3.2 Device Ratio Sweep
- 5.3.3 20µ Devices, Delay to rising edge
- 5.3.4 10µ Devices, Delay to rising edge
- 5.3.5 CMOS Gate Delay - improved
- 5.3.6 CMOS Gates - Analogue Functions
- 5.4 Mixer Design
- 5.5 Monte-Carlo Simulation
- 5.6 Low Noise Design
- 5.7 Modelling of Bipolar Devices
- 5.8 Timing
- 5.9 Confidence in Results
- 5.10 Self Assessment
- 5.11 Summary
5.1 Concepts
5.1.1 Top Level Design
Circuit simulation is divided into two main areas, high level and low level. High level simulation, typified by the various VHDL (Very High-level Design Language) approaches is described elsewhere in this course. More recently, analogue circuits have been designed using AHDL ( Analogue High-level Design Language) and this will be described in this section. These approaches take the design at functional block level and integrate the circuit from there automatically. At most the designer may have a set of tables to define the performance of logic gates etc. in terms of delays. Issues such as power supply provision is dealt with automatically. The designer is not at all concerned with the internal workings of the block, which may be very complex, or may even be parameterised. In this latter case, the designer defines the size of a memory or similar element as the dimensions, in units of memory cells, eg. 1024 x 1024 (1Mb). The design language translates this into both the memory array and the driver and sense amplifiers. This is a very powerful technique for fast and accurate design, since all cells within the array are pre-characterised and known. It is very computer hardware and software intensive, but it has a high probability of first time success. Circuit simulation is at the top level and there is no need to go inside the blocks merely to have accurate behavioural models of them. Simulation is therefore fast and accurate. These generalisations are possibly less correct for analogue circuits, but only marginally so. There are many initiatives afoot to bring analogue design into the same methodology as digital design.
5.1.2 Low Level Design
It could be argued that high level design will not get the very best from the process in performance terms, even for digital circuits. For analogue, 'full custom' design is still the norm, although the AHDL techniques noted above have much to offer. However, circuit design at this level, either for the full chip or for the cells to be used in VHDL/AHDL remains essential.
The techniques include DC simulation, to determine the bias point, AC simulation to determine the small signal characteristics, Noise simulation, which is generally associated with AC simulation, and Transient simulation. AC simulation assumes that the devices are linear in performance about an infinitely small space around the DC bias point. This has its uses, and is usually very fast in simulation. Transient analysis takes care of the large signal cases, and includes non-linear effects. Therefore, the models need to be more accurate, as do the model parameters supplied to fit them.
5.1.3 Why Large Signal Simulation?
Small signal ("AC") simulators just do not work for digital circuits; nothing switches. "Microwave" simulators are either small signal, or, where large signal, do a mixed time and frequency domain analysis, again without indication of switching. Transient, ie. time domain, large signal, simulation can include square waves and sine waves and so is also useful for power amplifiers, mixers and large signal effects such as intermodulation and intercept calculation. Fast Fourier Transform (FFT) techniques enable examination of frequency response etc. in much greater detail than the time domain. There is a close analogy here between these simulated approaches and the real measurements, ie. use an oscilloscope for the time domain and macro features, use a spectrum analyser for the fine detail, albeit at the cost of loss of phase information.
5.2 What Simulators are Available?
- Device level simulators such as the many SPICE variants, and SABER, SPECTER. These are more applicable to smaller scale circuits, where performance is key, or to cell design for larger circuits.
- High level simulators such as VHDL and VERILOG. These are the 'big chip' tools.
SPICE Variants
Generic SPICE Cheap, no schematic entry, limit post processing
ISPICE Low cost package which is getting better pre- and post processing
TSPICE Packaged with L-Edit
HSPICE Mid cost. HP Originated, well supported, used in Cadence/Mentor systems
PSPICE Mid cost. Very good pre- and post- processing. Fast, many features, mixed A/D mode, good support, near standard version.
5.2.1 Timing Simulation
High-speed circuits are best simulated as all-analogue components. Timing is then just a means of entering a suitable pulse or sine wave, or possible piecewise linear waveform, and observing the results. Very large circuits can be simulated in this way, eg. a full DDS (>5000 gates, 2 GHz)was simulated in this way. It took 16 hours on a 486DX2-66, or about 1.5 hours on a Pentium Pro.
Usually, it is better to simulate blocks, in reasonable times, and then confirm that they work together.
7.2.2 Three CMOS Gates
Fig 1 : Three CMOS Gates.
The circuit above will be used as an example of circuit simulation. It is a chain of three CMOS inverter gates.
5.2.3 CMOS Gate Delay
Fig 2 : CMOS Gate Delay.
The simulation above shows how the circuit should operate. In addition to the gate delays, it is possible to determine rise and fall times. Although of course such data is only as good as the model information fed in, most silicon manufacturers can now supply accurate model data, with a range of expected device spreads. From such information, it is possible to determine best and worst case gate delays and other aspects of performance such as power consumption.
5.3 Optimisation through Simulation
Suppose that we want the gates to run faster.We could:-
- Make the devices smaller, for minimum capacitance
- Make devices larger, for better drive
- Adjust area ratio?
In this case we sweep device size and sweep ratio of p-channel to n-channel to find the best point.
5.3.1 Device Size Sweep
Fig 3 : Three gate delays.Smaller devices are faster.
The sweep above indicates that smaller devices in this circuit are faster. We then sweep device size ratio. It is known that the p-channel FETs are more resistive and have lower gain than n-channel. Therefore, to approximately equalise the devices for drive capability, the p-channel should have twice the gate width of the n-channel. This gives a gate threshold voltage which is roughly central in the power supply voltage. This is not, however, the best circumstance for speed.
5.3.2 Device Ratio Sweep
Fig 4 : Device Ratio Sweep.
The plot above indicates that equal size devices give the best speed performance. In practice, this is the combination most used by IC designers for logic, since it is the most compact of the reasonable structures. It has the non-symmetrical threshold problem, but for internal gates this is not important.
5.3.3 20u Devices, Delay to rising edge
Fig 5 : 20u Devices, Delay to rising edge .
5.3.4 10µ Devices, Delay to rising edge
Fig 6 : Device Ratio Sweep.
The plots above show the difference between 20 micron and 10 micron gate width devices. The smaller devices are both faster and take lower power, so are preferred. Very small devices, however, would have been less efficient; each process tends to have an optimum point.
5.3.5 CMOS Gate Delay - improved
Fig 7 : CMOS Gate Delay - improved.
Finally, the plot above shows that optimisation has been achieved. Compare this with the similar plot at the start of this section.
5.3.6 CMOS Gates - Analogue Functions
In addition to their mainstream logic applications, CMOS gates may be used as amplifiers or mixers. DC bias is usually fed in through a high value resistor from the gate output. A typical monolithic single inverter stage will have +20dB of gain, and a 0.8 micron process will extend the bandwidth of the stage to several hundred MHz. NAND gates, similarly biased, will offer mixer functions. Lower noise will be achieved by dedicated designs, but for simple low cost RF circuits, CMOS has much to offer.5.4 Mixer Design
Mixer design is critical in RF circuitry.
Fig 8 : Mixer design.
The diagram above shows a bipolar transistor switching mixer, widely known by the name of its main protagonist as the Gilbert Cell. The transistors Q1 and Q2 provide a single ended to differential conversion to the input. The differential signals are then chopped between the output paths by the upper quad of transistors. These are driven by the local oscillator. Although it is possible to achieve results from this mixer using relatively low LO drive, it is more useful to switch the devices with a large signal. This will provide the lowest signal loss and best large signal handling performance, by driving the devices into a greater non-linearity.
MOS versions of this mixer have been published, although they lack the fundamental simplicity and accuracy of their bipolar counterpart. The bipolar base-emitter junction has a very wide range relationship with the current through the device which is not approached in MOS devices.
Fig 9 : Mixer design.
A modified version of the Gilbert Cell is the 'Micromixer' shown above, and also designed by Barrie Gilbert. This circuit has a different means of current feed, which under the right conditions can give excellent large signal handling at relatively low current levels.
Web Search Terms:
Web search for circuits and papers by Barrie Gilbert, of Analog Devices, USA.
5.5 Monte-Carlo Simulation
Monte Carlo simulation is offered in most design packages. It is a particularly useful technique in IC design where process variations occur. However, it must be carefully managed to produce meaningful results. The concept is quite simple; put in the allowed variations in parameters, and set the computer to find all possible solutions using these variations. This of course may take many successive simulations, and may even then not find the true worst cases. The variations imposed within the limit set are random, hence the 'Monte-Carlo' name.Most simulators offer a variation on the theme where some parameters, typically say resistor values, can be linked. Thus, for a given batch, slice or chip, all resistors of a particular type will have both a variation in value which tracks with all other similar resistors, and a totally random element, usually much smaller. This facility is primarily of use in design of data converters. The yield of fully accurate parts from functional parts may be predicted using Monte-Carlo techniques. This enables acceptable yields to be achieved even though the process accuracy when measured is barely acceptable. The reason for this is that process parameter variation is measured, and the data supplied, as a variation over many wafers. The short-range variation between identical resistors in the same orientation and physically close together may be very much better than the overall variation. Monte-Carlo methods will indicate what limits are needed for accurate device yield.
Fig 10 : Monte Carlo Analysis of Filter Centre Frequency.
n samples =10
n divisions =20
mean =41399.4
sigma =41399.4
minimum =41399.4
10th %ile =38643.6
median =41573.9
90th %ile =44285.2
maximum =44948.6
The output from a Monte-Carlo analysis may take the form of an error bar graph as above, with a statistical listing, or may be in the form of a multi-pass output graph as below.
Fig 11 : Results of a 10 pass Monte-Carlo analysis of a low frequency filter.
Although these simulations refer to low frequency filters, the techniques are similarly applicable at RF
Additional Reading: On-line PSPICE manual, section on Monte-Carlo analysis.
5.6 Low Noise Design
Low noise RF design is a large topic in itself. The fundamentals are similar to low noise design at lower frequencies, but greater consideration should be given to matching. The choice of active device, and especially its operating current level, is also critical. The noise contributions from the active devices are described in other parts of this chapter. Broadly, there are two important classes of noise; the broadband or 'white' noise and the '1/f' noise terms. All devices exhibit both types to some degree, but generally 1/f noise is more of a problem in GaAs devices, where the detailed non-homogeneity is thought to be the source of the added noise, and in MOS devices, where the surface effects produce 1/f terms. Typical MOS devices exhibit a 1/f 'knee' at 250kHz, ie. below this frequency the noise is predominantly 1/f, and rises in level as frequency falls. GaAs has a lower knee, typically below 100kHz. Silicon bipolar devices have a 1/f corner at 100Hz, so that the level of noise is very much lower.An example of the measured cross-over between 1/f and white noise in MOS is shown below. Although this is an operational amplifier, this plot primarily shows the performance of the input transistors. The average noise level measured was -121dBm ) in a 500Hz bandwidth, ie. 8.9nV/rt.Hz, with a 1/f corner at 225kHz.
Fig 4 1/f and white noise performance of CMOS input stage.
The relevance of white noise is perhaps the more obvious. High noise levels in a device lead to high noise level in the system; this is often the limiting factor in a VHF or higher frequency environment.
Noise below 250kHz may not seem immediately relevant in an RF system. In the case of an RF amplifier which is in its linear operating range, this is true. However, in a non-linear stage such as a mixer, the 1/f component is modulated onto the output. Thus, 1/f considerations are important for overall system design. Similarly, oscillator devices in synthesisers modulate noise onto their outputs, so again 1/f terms are important in design. Overall system noise is the summation in vector terms of all these non-coherent noise sources. System design at this level is clearly not simple. Added to this are noise sources contributed through the circuit substrate when in monolithic form, plus of course cross-talk from other circuits. The monolithic environment is difficult to design in!
5.7 Modelling of Biopolar Devices
This section will consider:- Model types
- Model Parameters
- Defaults and their effects
- Measurements needed
5.5.1 Model Types
- Ebers-Moll. Simple, default condition for most models
- Gummel-Poon. Much more realistic
- Enhanced Gummel-Poon. This is the standard form in use
5.5.2 Main Elements of Model Bipolar Transistor Parameters
The parameters and defaults below are taken from the PSPICE set, although others are similar.
| Model | Parameters Description | Units | Default |
|---|---|---|---|
| AF | Flicker noise exponent | 1 | |
| BF | Ideal maximum forward beta | 100 | |
| BR | Ideal maximum reverse beta | 1 | |
| CJC | Base-collector zero-bias p-n capacitance | farad | 0 |
| CJE | Base-emitter zero-bias p-n capacitance | farad | 0 |
| CJS | Substrate zero-bias p-n capacitance | farad | 0 |
| EG | Bandgap voltage (barrier height) | eV | 1.11 |
| FC | Forward-bias depletion capacitor coefficient | 0.50 | |
| GAMMA | Epitaxial region doping factor | 1.00E-11 | |
| IKF | Corner for forward-beta high-current roll-off | amp | infinite |
| IKR | Corner for reverse-beta high-current roll-off | amp | infinite |
| IRB | Current at which Rb falls to halfway | amp | infinite |
| IS | Transport saturation current | amp | 1.00E-16 |
| ISC | Base-collector leakage saturation | amp | 0 |
| ISE | Base-emitter leakage saturation current | amp | 0 |
| ISS | Substrate p-n saturation current | amp | 0 |
| ITF | Transit time dependency on lc | amp | 0 |
| KF | Flicker noise coefficient | 0 | |
| MJC | Base-collector p-n grading factor | 0.33 | |
| MJE | Base-emitter p-n grading factor | 0.33 | |
| MJS | Substrate p-n grading factor | 0 | |
| NC | Base-collector leakage emission coefficient | 2 | |
| NE | Base-emitter leakage emission coefficient | 1.5 | |
| NF | Forward current emission coefficient | 1 | |
| NK | High-current roll-off coefficient | 0.5 | |
| NR | Reverse current emission coefficient | 1 | |
| NS | Substrate p-n emission coefficient | 1 | |
| PTF | Excess phase @ 1 / (2n.TF)Hz | degree | 0 |
| QCO | Epitaxial region charge factor | coulomb | 0 |
| RB | Zero-bias (maximum) base resistance | ohm | 0 |
| RBM | Minimum base resistance | ohm | RB |
| RC | Collector ohmic resistance | ohm | 0 |
| RCO | Epitaxial region resistance | ohm | 0 |
| RE | Emitter ohmic resistance | ohm | 0 |
| TF | Ideal forward transit time | sec | 0 |
| TR | Ideal reverse transit time | sec | 0 |
| TRB1 | RB temperature coefficient (linear) | DegC-1 | 0 |
| TRB2 | RB temperature coefficient (quadratic) | DegC-1 | 0 |
| TRC1 | RC temperature coefficient (linear) | DegC-1 | 0 |
| TRC2 | RC temperature coefficient (quadratic) | DegC-1 | 0 |
| TRE1 | RE temperature coefficient (linear) | DegC-1 | 0 |
| TRE2 | RE temperature coefficient (quadratic) | DegC-2 | 0 |
| TRM1 | RBM temperature coefficient (linear) | DegC-1 | 0 |
| TRM2 | RBM temperature coefficient (quadratic) | DegC-2 | 0 |
| T_ABS | Absolute temperature | DegC | |
| T_MEASURED | Measured temperature | DegC | |
| T_REL-GLOBAL | Relative to current temperature | DegC | |
| T_REL_LOCAL | Relative to AKO model temperature | DegC | |
| VAF | Forward Early voltage | volt | infinite |
| VAR | Reverse Early voltage | volt | infinite |
| VJC | Base-collector built-in potential | volt | 0.75 |
| VJE | Base-emitter built-in potential | volt | 0.75 |
| VJS | Substrate p-n built-in potential | volt | 0.75 |
| VO | Carrier mobility "knee" voltage | volt | 10 |
| VTF | Transit time dependency on Vbc | volt | infinite |
| XCJC | Fraction of CJC connected internally to Rb | 1 | |
| XCJC2 | Fraction of CJC connected internally to Rb | 1 | |
| XTB | Forward and reverse beta temperature coefficient | 0 | |
| XTF | Transit time bias dependence coefficient | 0 | |
| XTI | IS temperature effect exponent | 3 |
Clearly bipolar modelling is a complex issue. Ideally, the manufacturer's data is complete and in a form which may be fed into the model. Where this is not the case, defaults must be used, although of course this may lead to inaccuracies.
Suggested reading
Read Machado Chapter 8 Bipolar Modelling
5.8 Timing
- Where standard, characterised blocks are available, digital simulation mode will shorten runs
- Interface with analogue simulation is easy
- But fine detail data may be lost
5.9 Confidence in Results
- Can only be built with experience
- Only as good as the models and model parameters
- No real frequency limit, except model validity
- Where extract from layout is used, resistor and capacitor parasitics can be built-in to simulation
5.10 SAQ
Simulate a circuit taken from an existing publication, eg. by B. Gilbert as suggested above. Compare the results with those reported. Prepare you data from web sources/others.
5.11 Summary
Circuit simulation at the transistor level is vital to the understanding of circuit operation. Widely available circuit simulation packages can give a very good approximation to the final circuit outcome. Optimisation of the circuit is possible, without the expense and time delays involved in multiple process runs.
Of the SPICE flavours, PSPICE is an industry standard; others are HSPICE and to a lesser extent SABER. The bipolar models are very good and should give very accurate simulations, as bipolar devices, except at the smallest lateral dimensions, are near-ideal in their characteristics. MOS models, especially the most recent, are also very good, at least down to channel lengths of 0.5 microns. However, much work continues to be reported in this field, and the devices rapidly become non-ideal at small dimensions.
Accurate parameters are key to good circuit simulation. Clearly, where a manufacturer supplies very comprehensive data with typical maximum and minimum values and temperature coefficients, confidence may be higher than if little data is supplied.
Cadence and Mentor interface to PSPICE, but use their own SPICE flavours.
There is no obvious sign of a successor to SPICE although SABER is sometimes said to be a successor. In many respects it is a parallel, and inevitably similar, path.