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Communications IC Architectures

Unit 6: Direct Digital Frequency Synthesisers

Unit Contents

• 6.1 Introduction
• 6.2 The DDS Concept
• 6.3 Spurious Output Terms
• 6.4 Spurious Output Frequencies
• 6.5 Digital Sampling - Rolloff
• 6.6 DDS Improvement Potential
• 6.7 Design Example
• 6.8 Performance Summary
• 6.9 The Practical Improvements needed in DDS
• 6.10 The future
• 6.11 Self Assessment
• 6.12 Internet keywords

6.1 Introduction

DDS is very correctly described as synthesis, in that the analogue waveform is literally synthesised on a point by point basis. This is illustrated in the diagram below.

Notable advantages of the DDS technique are:-
 

• Fast Frequency Hopping, as there is no loop settling time - no loop!
• No tune-up required; the function is almost all digital.
• Very broad frequency range is available from a single device, e.g. 1Hz to 500MHz as shown below.
• Very fine frequency increments are possible, .001Hz has been reported.
• Against the DDS is the high spurious level in the output; means of overcoming this will be described below.

6.2 The DDS Concept

Fig 1: The DDS Concept

At the left of the diagram, a frequency setting word is shown as an input. This is typically a very wide binary word, say 32 bits. The significance of this will be shown below. This information is fed to a block described as a phase accumulator. In this digital block, the word applied is added to the sum at the clock intervals. The resultant output word, limited to say 12 bits in length, is applied to a ROM look-up table. The ROM contains the co-ordinates of a sine wave, coded either for 360 degrees, 180 degrees or even 90 degrees. Each of these has its merits - see box below.

From the ROM, the digital word is applied to a fast digital to analogue converter (DAC). This reconstructs, i.e. synthesises, the sine waveform.
 

How Many Degrees?

At first, it might seem that the ROM should contain 360 degrees of waveform. This would be the ideal case, but very fast ROMs tend to be limited in operating speed by their size.  Roughly, twice the complexity equals half the speed. At the other extreme, clearly 90 degrees is the minimum. However, a little thought will show some problems.  If the ROM starts at 0 and goes to 90 degrees, how are the end points taken care of? Phase and amplitude inversions, necessary for the 90 degree ROM, would produce ambiguities, which in a fast system cannot be timed out. Instead, coding is taken as points just cannot be timed out. Instead, coding is taken at points just above zero and just below 90, so that phase an amplitude inversion gives a full 360 degrees smoothly.  
Returning to the sine wave synthesis,:-

The sinewave equation is:

This can be mathematically modelled, using say Mathcad.

Fig 2 : A sinewave sampled at 1024 point oer cycle

The mathcad representation of a sinewave is shown above. This is digitised at a resolution of 1024 points per 360 degrees. This is a high resolution and is difficult to achieve in a fast DAC.

Fig 3 : Three bit amplitude quantisation

For illustration, the plot above shows the effect of digitisation to 3 bits, i.e. 8 levels. The output is only very approximately a sine wave.

Fig 4 : Spectrum of a digitised (m=3 bits) sinewave

The Fourier analysis shows that the output spectrum has many discrete lines as above. The fundamental frequency is the largest, but in this idealised case many harmonics exist.   Between the harmonic frequencies, there is no output, i.e. the noise level is very low.
 
 

Fig 5 : Random error up to +/- 0.5

In contrast, the plot above includes the effect of a random +/- 0.5 LSB error on each step. This is of course much worse than any practical system, but illustrates the point.
 
 

Fig 6 : Spectrum of noisy reconstruction

The Fourier transform in this case is much noisier, although the relative size of the fundamental is maintained. Some of the harmonic energy is spread out, so the average fundamental to harmonic/noise signal is slightly improved.

Both plots above were for output frequencies which were exactly related to the clock frequency, i.e. ¼ of it.
 

Fig 7 : Spectrum of frequency "4.1"

In contrast, the figure above is for an output frequency which is not harmonically related to the clock. In this case the output is 1/(4.1) of the clock. The spectrum is smeared out in much the same way as the addition of noise to the steps. This is due to the finite amplitude quantisation, and is a fundamental limitation of the DDS technique.
 
 

6.3 Spurious Output terms

In relatively low speed circuits, very large ROMs are possible at little compromise in performance. However, where clock speeds are much higher, say 1GHz or more, the ROM size is an issue. In most technologies, at these speeds, ROM size and ROM access time are closely related. Thus, increasing the amplitude or phase resolution by one bit doubles ROM size and hence doubles access time. This produces a major design compromise.

Finite quantisation has been seen to cause 'noise' in the output as seen in the illustrations above.

The DAC is usually the main cause of spurious outputs, since it is the least ideal component in the system. The comments above on the ROM apply to the DAC at least for the amplitude terms. Strictly, if the DAC is not capable of updating in the time available, then it also contributes a phrase error term. It also very commonly exhibits 'glitch' in its output, which adds further random-like energy to the output spectrum.

Amplitude quantisation noise, due to the finite number of quantisation levels available is given by:-

-(6.02 Na + 1.76)dB

relative to the wanted  output, where Na  = No. bits of amplitude quantisation.

Phase truncation also contributes a term:-

= -(6.02 Nø +3.922) dB

where Nø  = No. bits of phase quantisation. Thus, amplitude quantisation is the most important term but phase cannot be neglected. It is usual to provide one more bit of phase information than amplitude, so that the phase term may be practically ignored, since it is then >8dB below the amplitude terms.
 

6.4 Spurious Output Frequencies

The important parameters for the DAC are linearity and settling time. Any non-linearity is translated as spurious frequency energy.

If the DAC is unable to settle to a final output within the clock time available, this also represents an error. It may be that the DAC has, say, 10 bits; but if the settling is only to an 8 bit equivalent in the clock period, then the DAC is effectively an 8 bit device.

The maximum spurious amplitude is -6.N dB below the wanted signal
- where N is the DAC linearity in bits. Strictly we should add the 1.76dB figure to this, but practical systems are rarely so effective.
The spurious calculations on DAC linearity have much in common with the linearity predictions which may be made for ADCs in receiver applications.

6.5 Digital Sampling Rolloff

A
  Degradation = {sin(Pi FDDS/Fclk)/ (Pi FDDS/Fclk)}

Fig 8 :

The effect of this on the potential amplitudes is dramatic when viewed over a wide frequency range. The plot above assumes a 1GHz clock rate. At 1 GHz output frequency, the output amplitude would be identically zero, while at frequencies above 1GHz, the amplitude maxima would be low. This effect is only from sampling; practical DACs would give further degradation.

DDS devices have been reported as working in the second lobe, i.e. between 1GHz and 2 GHz as above. However, the plot makes it clear why this is impractical; the amplitude reduction is usually unacceptable.
 

Fig 9

More realistically, the amplitude roll-off should be in the first lobe, and when compared with other synthesis methods, the DAC gives excellent amplitude control. The plot above shows this, while the table below lists the figures in detail, for a 1GHz clock. Other systems may be normalised to these figures.
 
 

Fig 10 : Signal Harmonics and Aliases

The spurious lines in the spectrum also limit operation to the first lobe in practice. The plot above illustrates a simple example. The first image is at a frequency equal to the (Fclk-FDDS). Clearly at FDDS=Fclk/2, the output and its image are identical in amplitude and frequency, and therefore not separable by filter methods. A more practical upper frequency bound is Fclk/3, i.e. low pass filters may be built to eliminate the image, now at or above 2.Fclk/3.

6.6 DDS Improvement Potential  

There are five main types of DAC error. These are:-
- Offset Error
- Scale factor error
- Linearity error
- Non-monotonicity
- Glitch Content.

Of these, offset and scale factor errors are really unimportant in the context of DDS. Good linearity implies monotonicity, so it is not a design constraint in itself. Glitch content is important, and design for low glitch is essential. This will be dealt with in a separate chapter.
 
 

6.7 Design Example  

Fig 11 :

The block diagram is shown above. To the left is a 31 stage 'pipelined' accumulator; this will be described in detail below. The frequency is set by a 30-bit binary word. Parallel loading is used to maximise loading speed. The block marked 'triangle generation' produced a digital triangle waveform, which the ROM converted to a sinewave as described above. Two output DACs were provided, for phase and quadrature output signals.
 

One bit of the 32-bit accumulator is shown diagrammatically below.
 
 

Fig 12 : Bit level block diagram

It consists of an input latch, level-shift stage, a full sum/carry adder and two latches, one for accumulation and one for the pipelining of the data to the next stage of the accumulator.
 

Fig 13

An example is the half-adder circuit shown above. Fully differential, low voltage swing (250 mV) logic was used throughout the device. The 1-micron bipolar process had peak Fts of 22 GHz. Under the bias conditions defined by the circuits used, Ft was approximately 15 GHz. Base resistance was typically 220 ohms, with a collector-substrate capacitance of 30 f F and collector-base capacitance of 14 f F.

Pipeline latching of the accumulator was used, as shown above. Also notable above was the array of deskewing latches, which provided accurate timing delay. Pipelining of the data input to the input latches was omitted, since it was only of significance during the period of frequency transition.

The XOR outputs could be switched directly to the DAC, to give a triangle output. Alternatively, the data could be streamed out through a parallel to serial converter for test purposes. Similarly, input data to the DACs could be streamed in through a serial to parallel converter also on the chip, for DAC test purposes.

The ROM size chosen was 896 bits, arranged as 2 x 64 x 7 bits, which, with amplitude and phase inversion, was equivalent to 8 amplitude bits and 256 time increments, i.e. it is square. There was a strong case for a doubling, at least, of the number of time increments, but SPICE-predicted access times precluded that option.

Fig 15 : Chip

The chip photo is shown above. The large block which is curved around the right side is the accumulator. The very densely packed area just above the centre is the ROM array, while the DACs are to the left.
 

Limitations and spurs

The limitation of a synthesiser of this type comes primarily from the truncation of the output frequency word, in both the ROM and the DAC. The provision of a relatively long (30-bit) phase word avoided problems from this source. Because very fast DACs are limited in achievable accuracy, they are the major limitation in this design. The effect of truncation of the digital word is the production of spurious output spectral lines. The magnitudes and spectral positions of these lines are described theoretically in References 5 and 6. The ROM design was also a compromise. A very large ROM would ideally be used, to give the very best representation of a sinewave, with a large number of time increments. However, in practice, limitations are imposed by the technology on the accurate word length that can be achieved. In addition, it should be realised that the critical parameter is the DAC accuracy achieved within the permitted settling time. At very high clock speeds, this is necessarily very short. There is a compromise between a very fast DAC of limited resolution, as here, at eight bits, and a much slower DAC of, say, 12 bits or more. As the latter device will almost certainly need some form of post-process trimming, it will inevitably be slow and hence will severely limit the maximum output frequency available. In most IC processes, eight to ten bits represents the limit of inherent component matching accuracy on-chip.

An example of the output at exactly ¼ of the clock frequency, where spurs are minimised, is shown above. Both the time and frequency domain plots are very clean.

Fig 17

A more realistic representation of the output is shown above, at a frequency which is not subharmonically related to the clock. The spurs are at all the frequencies described by the equations above, and at a worst case amplitude of -6N dB, although in this case the plot suggests that the DAC is not quite achieving the full 8 bits.

Although this device has a level of spurious signals that would make it unacceptable as a local oscillator in a high-performance single-frequency radio receiver, it has a frequency-hopping performance that makes it about five orders of magnitude faster than that of a loop synthesiser, a valuable characteristic for radar and EW. This is illustrated below.

Fig 18: Frequency Hopping

channel 1= 40mV/div, channel 2= 20mV/div, timebase = 20ns/div

The plots above show the output frequency hopping from 25 MHz to 8 MHz, with a delay of approximately 18 ns. There is a further small delay of about 3 ns between the frequencies, as the new frequency data steps through the input register.

6.8 Performance Summary

Fig 19 : Multifunction DDS

A more technically advanced DDS is shown above. Although slower, this device offers many more functions, such as I-Q modulation and phase control of the output. It is possible to produce a single sideband modulator chip using DDS techniques, since both phase and quadrature outputs are available from the majority of devices. The phase relationship is accurate and independent of frequency.

6.9 The Practical Improvements Needed In DDS

Fig 20 : Integration to form sine waves

One means of replacing the ROM is just to use a triangle output. The ideal triangle wave consists only of odd harmonics, so in any system where very broad frequency coverage is not needed, a triangle wave and filters will suffice. Alternatively, as above, digital integration techniques may be used to obtain closer approximations to the sinewave.

Fig 21 : Digital integration for the DDS

 
A means of achieving the same result, essentially using a similar technique, is to employ a digital filter. In the diagram above, a simple digital filter has been used to integrate the triangle to a very acceptable sinewave. This is a mathematical representation, but could be employed in practice, since the FIR filter chosen uses only the coefficients 0 and 1. This makes digital multiplication in the filter very easy, and therefore fast. Typically, DSP filters are much more complex and hence much slower.

The other alternative is to use phase locked loops as filters. There are many possible architectures, of which two are shown here. In general, the PLL will much increase the potential frequency hop time, but will act as a very good filter of the spurs. A DDS-PLL combination will also usually retain the fine frequency increments of the DDS, since the PLL bandwidth may be several, or many,kHz, while the DDS will give sub-1Hz increments within that range.

Fig 22 : phase locked loop DDS

In the loop shown above, the DDS output is effectively multiplied by the N of the PLL divider. This shifts the DDS range potentially into the microwave region. However, the PLL loop filter will reduce the off-frequency spur level substantially. In-band, however, the spurs remain and are effectively also multiplied by the loop, so some modulation of the oscillator is to be expected. Nevertheless, the oscillator itself acts as a filter due to its limited slew rate. This is potentially a very attractive system for microwave synthesis.
 
 

Fig 23 : Offset phase locked loop DDS

In the second variant, the DDS acts as a variable reference. This is the case where very fine frequency increments are needed in the PLL, without compromise of its frequency shift capability. Conventionally, a 1 Hz step size would require a loop bandwidth of much less than 1 Hz, i.e. the rate of frequency change would be severely limited. In the system shown above, the PLL loop bandwidth can be relatively large, while the DDS gives the fine increments.

6.10 The Future

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