Communications IC Architectures
Unit 8: Analogue to Digital Conversion for Radio
Unit Contents
- 8.1 Analogue to Digital and Digital to Analogue Conversion
- 8.2 ADCs in Radio Applications
- 8.3 ADC Concepts
- 8.4 The Parallel or 'Flash' ADC
- 8.5 DACs and Successive Approximation ADCs
- 8.6 Accuracy Issues
- 8.7 Self-Assessment
- 8.8 In Summary
8.1 Analogue to Digital and Digital to Analogue Conversion
ADCs and DACs are widely used in many applications. However, as other parts of this module have shown, there are specific needs within digital radio applications where ADCs and DACs have a role to play which stretches the limits of conventional devices. Increasingly, these functions are seen as part of greater 'systems on a chip'. This, with the limiting performance, is a near-incompatible combination.There are some mitigating factors, and it is these which will form the first parts of this section.
8.2 ADCs in Radio Applications
To some extent this topic has been covered in the early chapters of this module. The need is for very wide instantaneous dynamic range, i.e. to achieve wide signal operating levels, the ADC must convert all bits essentially simultaneously, although within a time defined by a sample and hold is acceptable. Two stage ADCs, in the sense of one stage early in the radio and a second later, are unlikely to achieve the full dynamic range requirement.One essential element however may be taken as a mitigating factor. Although the input amplifier bandwidth must be adequate for the input signal, the sample rate need only be twice the data rate required. For example, if a digital radio IF operates at 100MHz, the ADC sample rate should simplistically be 200MHz or greater. However, if the information bandwidth of the signal is say 200kHz, then the ADC sample rate need only be 400kHz or greater. The input stages of the ADC must handle the 100MHz signal, but need only be flat in response over the 200kHz of the bandwidth. There is still a negative point; if the sample rate is 400kHz, then the output data is at this rate, and cannot be usefully converted back again. The signal is said to have been converted to baseband. A minor variant is to use a further IF at say 200kHz, but this would in most cases introduce unacceptably low IF bandwidths.
Clearly very high accuracy converters are not compatible with high sample rates, but sample and hold circuits may be. This is the means of matching up the two frequency ranges.
DACs, typically for the synthesiser, especially DDS, have related problems. The realtionship between accuracy and spurious output levels has been described in the early chapetrs of this module. When compared with a 'normal' DAC, the main factors for DAC specifications are :-
- Accuracy, i.e. linearity. This is essential in a DAC for DDS.
- DC offset. Although often important in other DAC applications, offset is not usually important for DDS.
- Scaling factor. Again unimportant for DDS.
- Speed. DDS requires the best speed at a specified accuracy. This is the key element in the design; high speed to a lower accuracy will not give a good DDS result.
8.3 ADCs Concepts
Conversion from analogue to digital form is a key issue in digital radio receivers. The section covering receiver design indicated the resolution and accuracy constraints on the ADCs. Broadly, the dynamic range of the receiver is 6NdB, where N is the number of bits of accuracy of the ADC, at the sampling frequency. This means that a receiver ADC should be 17 bits or more.In the same way, and for the same numerical reasons, the DAC in a direct digital synthesiser should also give a spurious level 6NdB below the carrier. The relationship is more complex, since digitally generated sidebands on the local oscillator do not necessarily translate into the signal path. However, practically, 6N for the DDS-DAC should be greater than 70dB. These are demanding designs.
Generally, in each case, circuit techniques have been adapted to mask the effects of the ADC or DAC in each of the cases, since the full specifications are not achievable at the frequencies of most interest.
8.4 The Parallel or 'Flash' ADC
Fig 1 :The Parallel or 'Flash' ADC
The diagram above shows a very simple ADC concept, although one which remains in favour for the fastest circuits. At the left of the diagram is a resistor chain which defines a set of 2n -1 reference levels. A set of comparators compares the incoming signal with those reference levels under the control of a clock signal. The comparator outputs are in a simple code, usually referred to as a thermometer code, i.e. it fills with 1's from the bottom. Additional gating is often provided after the comparators as shown to avoid ambiguities from comparator outputs. The thermometer code is translated in a ROM to a conventional binary, or sometimes grey code.
Issues to be addressed in this circuit are :-
- The resistor ladder, which must give accurate levels at its reference points
- Comparator design. They must be fast and unambiguous. Hysteresis may be a help in some cases.
- Comparator offset. Random process variations limit the overall accuracy which can be achieved.
- Logic for ambiguity resolution. In the limit, and individual comparator can see an exactly balance input. Its output code may enter a metastable state, so logic may be useful to determine the exact state for the ROM drive.
- ROM access times can also be a limitation.
Fig 2 : The Parallel or 'Flash' ADC
Where more bits are needed, there are many versions of 'series-parallel' ADCs such as the above. The first ADC converts the larger parts of the signal, then subtracts the value from the input signal, for a second conversion. The parallel ADC requires a minimum of 2n -1 comparators, and so requires a large chip area. Series parallel approaches reduce chip area, at a cost in the additional delays and hence operating speed reduction needed. Also, most of these schemes imply additional analogue accuracy at high speed. This is not easily achieved. At very least, in the above structure, the sample and hold is a very demanding analogue design.
8.5 DACs and Successive Approximation ADCs
Fig 3 : DACs and Successive Approximation ADCs
The diagram above is actually of a DAC, of a simple type which may be used in a loop for successive approximation. The DAC operation is fairly simple. The bits are set to 0 or 1 as appropriate. This determines, through analogue switches, the voltage at the output. The analogy of this DAC with the parallel ADC is clear. However, there are practical limitations. The switches must be of very low offset voltage level, i.e. CMOS is preferred. The switch on resistance is also a factor in the operating speed of the DAC, so operation may not be fast. Increasing switch size to reduce on resistance adds to the parasitic capacitance, thus slowing the operation.
In a successive approximation ADC, the data fed to the bit inputs is from a register which may be clocked up or down under control of a comparator. The comparator compares the analogue input voltage with the DAC output, so that after several cycles, typically N+1 for an N bit ADC, the DAC output is identical to the analogue input. The bit lines are then the ADC output code.
(image removed)
For dynamic accuracy, the input should be held in a sample and hold. A variant of this circuit uses simpler control logic which steps up or down under clock control. This is the 'tracking' converter, which can follow small analogue steps very fast, but is more limited for large analogue excursions.
Fig 4 :Analog Devices
Derived from Analog Devices
A more complex DAC is shown above, in this case in bipolar circuitry.
Current sources in bipolar may be very conveniently switched, with good accuracy.
Careful ratio arrangements for the current sources are needed to ensure correct
operation over temperature.
Fig 5: DACs and Successive Approximation ADCs
Derived from Mitel Semiconductors
The chip photo above, a 2GHz clock rate DDS, shows in the outlined area
the two DACs. In this chip, speed was all-important, so the DACs were limited
to 8 bits. More importantly, they were on the same chip as the digital parts
of the circuit. This could have lead to power-supply interference problems,
especially in the current hungry ECL. This was dealt with in several ways. The
full circuit, including the DACs, was synchronous. Hence, any feed-around of
transient currents should have been minimal during the important settling times.
The circuits were designed with good power supply rejection, i.e. differential
configurations were used. Finally, very wide power tracks, separated for the
digital and DAC feeds, were used. Since feedthrough problems of this type are
notoriously difficult to predict, where possible, all precautions should be
taken.
The reason for the single chip approach was just that calculations showed that
data skew at the 2GHz+ clock rate would prevent accurate timing of the interface
between two chips.
The DACs in this example were arrays of matched current sources, with an interstage
current divider. Glitch output was minimal, less than 2ps-V.
Fig 6 : Digital Input Code
Derived from Analog Devices
A similar structure is shown in the diagram above for processes where
accurate switch devices are possible. This is the 'R-2R' ladder network, in
this case with a segmentation into two sections and a weighting resistor bin
the middle.
Fig 7 : Digital Input Code
Derived from Analog Devices
A full successive approximation ADC is shown above. The diagram includes
the DAC, comparator and the control logic, in this case with an option for bipolar
operation
Fig 8 : Digital Input Code
Derived from Analog Devices
The fastest DACs use switched current sources. These may be uniform in current level, or may just be used for the most significant bits as above. The advantage of this structure is that the largest bits may be made as equal as possible, to avoid switching transients known as glitches. The lesser bits are then generated in a more compact DAC, although of course speed remains important.
Fig 9 : DACs and Successive Approximation ADCs
derived from Philips
8.6 Accuracy Issues
8.6.1 Dynamic Element Matching
For more accuracy than the baseline process is capable of achieving, there are circuit 'tricks'. One of the best of these is 'Dynamic Element Matching', originally by Philips. The concept is that two current sources are switched between two outputs. Provided that the effective current measurement time is over several switching clock periods, the two output currents are very well matched, since they are averaged. The scheme may be extended as above to multiple levels, and may also be generalised to N current sources and more complex switching arrangements. It is possible using this technique to achieve matching sufficient for 16 - 18 bit converters in fast bipolar processes, thus combining speed and accuracy.
Fig 10 : Dynamic Element Matching
8.6.2 Sigma-Delta Converters
The class of ADCs and DACs which have had the most attention in recent times
is the 'Sigma-Delta' type. There are many variations on this architecture, just
two of which are shown above. The concept is simple, although the realisation
is often less so. Clearly, if a DAC has only two output levels, which of course
need to be stable, then it may be made with unlimited accuracy. If then it can
be oversampled, i.e. its output compared with an input, and the resulting error
term fed back, then a multi-bit converter may be achieved. The bulk of the operation
occurs in digital form, where accuracy is not impared. In the limit, converters
of >20 bits are possible, but since this requires a great deal of oversampling,
the resulting ADCs and DACs are very slow. Filters help, and higher order oversampling
may also improve speeds, but generally this is not a fast converter class.
8.7 Self-Assessment
Suggested reading
Read chapters 19 and 25 in Machado, also the Analog -Digital Conversion Handbook, by Analog Devices. Find some of the recent papers from IEEE Journal of Solid State Circuits.
SAQ
What is the fastest ADC you can find with 16 bits or more? Draw up a 'State of the art ' graph for ADCs and DACs, with axes of accuracy and speed.
Some paper references are:-
P H. Saul, M.S.J Mudd
A Direct Digital Synthesiser with 100MHz output capability
IEEE Journal of Solid State Circuits Vol 23 No 3 June 1988 pp 819-821
A K Joy et al
A Comparison of GaAs HJBT .....Analog-to-Digital Converters
IEEE Journal of Solid State Circuits Vol 24 No 3 June 1988 pp 609-616
P H Saul , D G Taylor
A High Speed Direct Frequency Synthesiser
IEEE Journal of Solid State Circuits Vol 24 No 1 Feb 1990 pp 215-219
P H Saul et al
Single Chip 500MHz Function Generator
IEE Proceedings -G Vol 138 No 2 April 1991 pp239-243
Internet keywords
Analog, digital, ADC, DAC, Analog Devices, Burr-Brown.
Oversampling, sigma-delta.