Communications IC Architectures
Unit 9: Layout Aspects
Introductory text....
Unit Contents
- 9.1 Layout Considerations for R. F. Design
- 9.2 Bond Pads
- 9.3 Active and Passive Devices
- 9.4 Self-Assessment
- 9.5 In Summary
9.1 Layout Considerations for R. F. Design
At its simplest level, R.F. layout need not be significantly more complex than low frequency analogue layout. However, as with low frequency analogue layout, design considerations should be very thorough.Most digital design is carried out through the use of standard cells. These may be fixed cells, or may be parameterised, for example for a ROM, where an array in a given case is N x M elements, and macros in the design CAD can generate this easily, with little user intervention.
Of course, there is still a need for the generation of the layouts of the standard cells, but this is usually carried out by the process vendor, and a library is supplied as part of the design kit. Very often, the inside of these cells is not made publicly available, so it is difficult to pick up practical design tips in this way.
In most digital chips, the emphasis is on saving chip area. Distribution of power rails may become an issue, especially in bipolar circuits, but in CMOS, individual circuit current is low. The sum may be high, and issues of 'ground bounce' need to be addressed, but in general digital design is relatively straightforward in layout, and often carried out at the macro level, with as much automatic layout as possible. The reason for this is minimisation of errors.
Low frequency analogue design is still much more 'hand crafted'. Automatic analogue design techniques do exist, and high level languages ( AHDL) but they are not yet the norm. The reason for this is that a typical analogue circuit has many different functions, while a digital circuit has a very limited set of possible functions.
Usually, layout area is not as critical for analogue circuits. More important are issues like noise, power supply rejection and avoidance of cross-coupling, either from other analogue circuits or from digital parts of the same chip.
Where very low noise circuits are required, all these issues are important,
especially coupling through the supply rails. It is important to rcognise that
many of these problems can be quantified. Coupling through the substrate is
more difficult, but estimates can be made.
9.2 Bond Pads
Fig 1 : Bond Pad with Protection Structures
Many process vendors offer a choice of bond pads. At lower frequencies, the use of a static protected bond pad should be regarded as mandatory; the process vendor will offer such pads. At higher frequencies, the decisions are more difficult. Typically, static protection pads include some series resistance, possibly hundreds of ohms. Although not an issue in a digital circuit, clearly this would seriously degrade a low noise amplifier. A better choice would have no series resistance, and minimal capacitance. Some vendors offer smaller 'R.F.' pads, with minimal capacitance. These are often round rather than square, and typically have fewer protection components.
Component matching is less often required at R.F. than at lower frequencies, although symmetry of layout where it exists in the circuit should always be considered.
Connections to the outside world are particularly problematic for R.F. chips.
The inductances and capacitances of the bond wires and lead frame usually give
a far from ideal R.F. environment. There are 'R.F.' packages where these effects
have been minimised, but they are expensive and little used in practice.
| Length | Resistance> | Self Inductance | Mutual Inductance | C to gnd | Lateral Cap | |
|---|---|---|---|---|---|---|
| Tracks | 1mm | 50 ohms | 0.5nH | 0.01nH | 50f | 50f |
| Bond pad | 100u | 500f to 4p | ||||
| Bond wire | ~5mm | 25mohm | 3nH | 1nH | 100f | |
| Leadframe | ~10mm | 25mohm | 3nH | 1nH | 500f to 2p | 300f |
The table above quantifies some of the parasitic components in the connections to the outside. The bond pad capacitance can reach 4pF unles R.F. pads are used. Self and mutual inductance terms are important, since coupling between adjacent pins can occur. At frequencies of >2GHz, the isolation between adjacent pins may be less than 30dB. It is sometime advisable to include grounded pin/bond wire/pad combinations as shielding between sensitive nodes.
9.3 Active and Passive Devices
Active devices for R.F. include GaAs FETs, silicon bipolars and NMOS and possibly PMOS transistors. Standard library types for a given process vendor can usually be adapted to the requirement, and are strongly advocated to avoid layout errors.
Passive devices include resistors and capacitors, which are routinely included
in both low and high frequency analogue circuits, and inductors, which are commonly
included in GaAs circuits, but less so in silicon because the losses are greater.
Some sample device layouts are shown below:
Fig 2 : NMOS transistor, designed to a 2 lambda rule set, for 0.8 micron process
One feature of many layout editors is the use of a 'lambda;' based rule set.
The designs are all based on a convenient unit, for example the gate of the
transistor above is 2 units wide. Then, at a given process foundry, this rule
may be interpreted as required. For example, this design may be used on a 0.8
micron process, so the 2 units wide gate would be processed as 0.8 microns.
This is primarily applicable to digital design, for easy transport of designs
between processes, but the designer should be aware of this facility.
Fig 3 : PMOS transistor
Similarly, a PMOS device is shown above. In this case, the device is surrounded
by an N-well, for correct polarity of conductors and isolation.
Fig 4 : Vertical NPN transistor
A more complex structure, not always available on MOS processes, is a vertical
NPN bipolar transistor, as above. Again, a recommended layout from the process
vendor should be used in this instance if possible.
Fig 5, Lateral PNP
Less good, especially in the R.F. context, is the lateral PNP shown above.
PNPs in general have not been well used in R.F. circuits, but new processes
offer Fts close to those expected from the NPNs, so interesting circuits might
be made in this respect.
Fig 6 : Polysilicon resistor
For R.F. applications, polysilicon resistors are preferred, since they are
deposited above the first oxide layers, and therefore have less capacitance
to ground and other nodes than a similar value junction resistor. This ensures
low parasitic capacitance. They are also voltage insensitive, although the temperature
coefficient can be quite high, and should be carefully calculated, especially
for the high sheet resistivities, which often have a negative coefficient.
Fig 7 : Poly1 - Poly2 capacitor
Capacitors formed between the poly silicon layers ( Poly1 - poly2) are also
preferred for R.F. applications. The reasoning is similar to that for the resistors.
A rough rule is that the capacitance to ground from the bottom plate of the
capacitor should be about 1/10 of the plate capacitance. Alternative sandwich
capacitors such as metal to metal are usually poorer in this respect, although
series resistance in the ploy1-poly2 type is an issue to be addressed.
Fig 8 : Inductor Layout
An inductor is the most difficult compromise in layout, and many papers have been written on this subject. The inductor above has some of the desirable features. These are:-
1. The centre is relatively open. Small turns add little inductance, just resistance
and capacitance.
2. The turns are closely spaced, for minimum overall size. It may be improved
by:-
3. Chamfered corners, although this is debated.
4. M2 instead of M1, because M2 is usually thicker and therefore lower resistance.
M2 is alos lower capacitance to substrate. M3, when available is often better.
This layout is from a chip where the M1 - M2 comparison is
the subject of an experiment.
5. Larger central hole, although this may compromise size.
9.4 Self-Assessment
Try some layouts.
Internet keywords
MOSIS, Hewlett Packard, Mitel, AMS, Tanner
Look for manuals for Cadence Artist and Tanner L-Edit
9.5 In Summary
Layout is a topic best learnt by doing. However, it is emphasised that calculation of all parameters such as parasitic capacitances and resistances should be regarded as mandatory for R.F. circuits.