Design for Signal Integrity
Unit 3.0: IBIS Fundamentals
In this unit we describe IBIS models at circuit level and explain why we use IBIS models as opposed to SPICE models in the simulation of printed circuit board performance.
IBIS stands for Input/Output Buffer Information Specification- in fact IBIS models are used to specify the electrical performance of the input circuits and output circuits of digital integrated circuits. They contain no information about circuit functionality- they are intended for use in the evaluation of the integrity of digital signals on a PCB. Because IBIS models are non-functional they are called behavioural models- they just model the electrical behaviour of devices.
The behavioural approach to simulation evaluates the electrical performance of the PCB and its associated semiconductor devices, rather than the functionality of the system . SPICE simulations may be used to produce detailed evaluations of the electrical and functional performance of the system but they can be very time consuming.
Behavioural simulations are much less time consuming and, most importantly, they reveal information about PCB performance directly. Another extremely important advantage of behavioural simulation models is that they are available from reputable integrated circuit manufactures free of charge. This is not the case for SPICE models, which may reveal detailed information about a manufacture's processes. Consequently, manufactures are often reluctant to release SPICE models for general use. In principle behavioural models are freely available, but in reality only a limited number of validated models are available. However, IBIS models are becoming available for a greater range of devices and it is anticipated that this trend will continue.
We shall start by considering the IBIS model of a simple CMOS logic gate.
Unit Contents
- 3.1 The IBIS Model of a Simple CMOS Logic Gate
- 3.2 The IBIS Model of a Typical CMOS Input Circuit
- 3.3 The IBIS Model of a Typical 2 State Output Circuit
- 3.4 Typical I/O Types
- 3.5 A Typical Tristate Output Stage
- 3.6 A Typical CMOS Input/Output Circuit
- 3.7 Why use IBIS Models
- 3.8 Summary
- 3.9 Supplementary Information
3.1 The IBIS Model a Simple CMOS Logic Gate
The circuit in Figure 3.1 shows how we represent a 2 input gate, showing the I/O buffers used in IBIS models.
Figure 3.1 A CMOS 2 input gate showing the Input/Output buffers used in IBIS models
Transistors TR1 and TR2 are the output buffer of the gate. When TR1 is on, TR2 is off and the voltage at the output pin is VDD. If TR1 is off and TR2 is on, the voltage at the output pin is VSS.
Transistors TR3 and TR4 form the input buffer of one of the inputs to the gate. Diodes D1 and D2 are voltage clamp diodes that ensure the input voltage is held between VDD+VFD and VSS-VFD if the gate input voltage moves outside the supply voltage range.
There is a second input buffer connected to the 2nd input of the logic gate in Fig 3.1.
IBIS models only represent the behaviour of the input/output buffers of integrated circuits. The functionality of the integrated circuit is effectively controlled by the functional block shown in Fig 3.1, and is not simulated during IBIS simulations.
The circuit shown in Fig 3.1 is simplified- it does not show IC package parasitics and die parasitics. We shall include these as we develop the IBIS models for logic gates.
An example of a simple IC package is shown in Fig 3.2
Figure 3.2 Pin to die connections in a simple IC
The IC die connection pads are connected to the IC pins using very fine wires. The values of lead resistance, lead inductance and package capacitance are different for each pin on the IC because the pin to die connecting wires are different lengths and different geometries.
The components on the die also have parasitic capacitance associated with them, so the model of say an input pin on even a simple IC, is quite complex. When we create an IBIS model of an IC we are creating equivalent circuits for each pin on the IC that is being modeled.
3.2 The IBIS Model of a Typical CMOS Input Circuit
The IBIS model on a typical CMOS input pin is shown in Fig 3.3
Figure 3.3 An IBIS Model of a typical CMOS input pin
R_pkg = "package" input lead resistance
C_pkg = "package" input lead capacitance
L_pkg = "Package" input lead self inductance
C_comp= die input circuit self capacitance
The circuit topology is the same for each input pin on the IC, but values of lead resistance, capacitance and inductance are different. Another complicating factor is that the values of the parasitics are different from IC to IC of the same type, which means there is a range of values for each input pin on the IC.
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3.3 The IBIS Model of a Typical 2 State Output Circuit
The circuit in Fig 3.4 is the IBIS model for a typical CMOS output buffer.
Figure 3.4 IBIS Model showing package parasitics and and die output capacitance
The meaning of the symbols is the same as in Fig 3.4, except that C_comp is now the die output circuit self capacitance.
Information about the output model switching performance is included in the IBIS file. This may be stated as a linear voltage ramp, dV/dt, for both the rising and falling edges of the wave form or included in tabular format. The definitions of IBIS model parameters and timing information is dealt with in more detail in the unit on IBIS files.
The output model shown in Fig 3.4, is for a simple CMOS 2 state output device. More complex I/O stages are in use, for example when a pin on an IC can be either an input of an output, depending on its use.
3.4 Typical I/O types
Examples of more complex I/O structure requirements are given in Fig 3.5 together with a brief indication of their application.
Figure 3.5 A typical microprocessor data bus system
The databus of a microprocessor system has been chosen to illustrate the need for input/output buffers of different types. Fundamentally a databus is bi-directional, that is data can flow in both directions on the bus. The microprocessor controls the flow of data and we shall now consider the type of Input/Output circuits associated with each of the devices in Fig 3.5
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Read Only memory (ROM)
- The read only memory is where fixed data is stored such as the system program and tables, etc. Data can only be read from ROM. However, it must be possible to disconnect the output stages of the ROM from the databus, when the ROM is not in use, to free the databus for other devices to use. The type of output stage required is referred to as a tristate output: the output stages can be effectively open circuited, or have a logic 1 or 0 on them, say 5V or 0V. The circuit arrangement for this type of device is shown in Fig 3.6.
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Random Access Memory (RAM)
- Data that changes while the system program is executing is stored in RAM. So data can flow into RAM from the data bus, or out of RAM onto the databus as the program executes. The circuits used in these operations are called input/output circuits. When the microprocessor program requires data to flow into RAM, the RAM I/O circuits are set as inputs. When data is required to flow out of RAM, the RAM I/O circuits are set as outputs.When RAM is not in use it is set to the high impedance state. The circuit diagram for this arrangement is shown in Fig 3.7.
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Input Devices
- Data flows into the system via input devices. Input buffers are like those shown in Fig 3.3 and interface the system to the external world. Data is read from the input devices under microprocessor control, so the output circuits of input devices are tristate output devices like those shown in Fig 3.6.
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Output Devices
- Data flows from the system to the outside world via output devices, under microprocessor control. Output devices have output circuit arrangements like that shown in Fig 3.4. Output signals to the outside world may be two state or tristate, depending upon the application.
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Pull Down Resistors
- The final components shown in Fig 3.5, are pull down resistors, which are used to connect the databus tracks to a reference potential, usually VSS or VDD in CMOS systems, to pull the databus to a defined potential when it is not in use, that is when all the output devices connected to the bus are in the open circuit mode (high impedance state), or the circuit is de-energised, for example in transit. Either pull down or pull up resistors may be used.
We have used the microprocessor model to show that several types of I/O arrangements are required, the diagrams below show the circuit arrangements for these I/O devices.
3.5 A Typical CMOS Tri-state Output Stage
Figure 3.6 A typical CMOS tristate output stage
In Fig 3.6 the transistors are driven so they switch in anti phase, when TR1 is on and TR2 is off, the voltage at the output pin is VDD. When TR1 is off and TR2 is on the voltage at the output pin is VSS. When the device is not in use both transistors are off and the output of the device is effectively open circuited. Protection diodes may now be included to protect the transistors from voltage spikes in this mode. Of course, both transistors are not turned on at the same time.
3.6 A Typical CMOS Input/Output Circuit
Figure 3.7 A typical CMOS Input/Output stage
A CMOS Input/Output stage is shown in Fig 3.7. The circuit consists of a tristate output stage combined with an input stage. When the pin is to be used as an input the tristate stage is put into the high impedance state and data is entered from the databus via the input transistors, T3 and T4. When the pin is to be used as an output data from the input transistors is inhibited by internal chip logic.
In order to simulate the behaviour of the above I/O buffer arrangement IBIS models must be created for them for each type of IC used in the simulation.
We shall consider IBIS model definition in the unit on IBIS files.
3.7 Why use IBIS Models?
We have described the circuit topology of several types of Input/Output buffers that are used in CMOS integrated circuits. The same I/O buffer topologies are used for a particular IC family. The I/O behaviour differs from IC to IC, even of the same type, due to parasitic elements associated with the IC packaging, IC manufacturing tolerances and environmental operating conditions. In addition the response times of the transistors in the I/O stages differs from IC to IC, even of the same type. When evaluating PCB performance, as opposed to system performance, we are only interested in those aspects of the PCB that affect signal integrity- that is the performance of tracks on the PCB that are critical for signal integrity. We are not concerned with system functionality. Consequently we can simulate critical PCB tracks at I/O level only, which makes simulation faster and simpler than full SPICE simulations.
We use IBIS models because they allow us to evaluate signal integrity on a PCB at I/O level only- which means we can evaluate PCB performance independently of system functional performance.
IBIS models are defined as behavioural models because they do not model an integrated circuits functionality: IBIS models only model the behaviour of the I/O buffer transistors and associated pin parasitic elements.
When we combine IBIS models with real electronic components and PCB parameters such as transmission lines formed by PCB tracks, we can evaluate the signal integrity of critical PCB tracks using simulation techniques.
3.8 Summary
In this unit we have described several types of input/output buffers used in CMOS integrated circuits.
We have briefly explained that the use of IBIS models allows the signal integrity on a PCB to be evaluated directly.
We have also stated that the use of IBIS models in simulations is simpler and faster than SPICE simulations.
It must be remembered that we have only considered CMOS I/O structures. However, IBIS models are used for other digital logic families, such as TTL and ECL.
3.9
Supplementary Information
Information about IBIS file specification and creation may be found at the following:-
IBIS (I/O Buffer Information Specification)
TI IBIS File Creation, Validation and Distribution Process SZZA034 (Texas Instruments) (pdf)