Printed Circuit Design
Unit 2: Bypassing and Decoupling
Contents
- 1 Introduction
- 2 PCB Power Requirements
- 3 Grounding Techniques for PCBs
- 4 The Capacitor at High Frequencies
- 5 Practical Decoupling and Bypassing
- 6 Decoupling Design
- 7 Summary
- Bypassing and Decoupling
1 Introduction
Decoupling capacitors are an important part of any digital printed circuit board design. These capacitors are connected between power and power return conductors (e.g. ground) to help stabilise the voltage delivered to active digital devices. When there is a sudden change in the current drawn by a particular device, decoupling capacitors provide a local source of charge so that current can be supplied quickly without causing the voltage on the power pins to dip suddenly. Boards with inadequate decoupling suffer from excessive power bus noise, which may cause signal integrity or EMC problems affecting the reliability of the product.
Printed circuit board decoupling is as old as printed circuit board technology itself. Early boards with one copper layer generally contained a large decoupling capacitor near the point where power came on to the board. Larger devices that were likely to exhibit a sudden change in the amount of current they required often had their own decoupling capacitors across their power pins.
The earliest printed circuit boards were built for analogue circuits. Analogue circuit designers were very familiar with noise sources and filtering, so power supply (or bus) decoupling was nothing new to them. Later, with the introduction of digital circuits, power distribution was no longer an integral part of the circuit design. Digital circuits required a supply voltage that was sufficiently stable (e.g. TTL at +5V), but the overall quality of the product was no longer tied to specific levels of power bus noise. As the number of digital printed circuit boards increased, printed circuit board decoupling became an afterthought. It was generally possible to build boards with a nominal amount of decoupling that operated flawlessly.
As the speed of digital circuits increased, more of the energy in power bus transients was at high frequencies. This forced designers to pay more attention to the decoupling capacitors they used and specifically to the equivalent series inductance of these capacitors and their connections to the board. A common practice in the 1970s and 80s was to put two decoupling capacitors on high-speed digital devices. One was a large-valued capacitor (known as a reservoir capacitor) to filter the lower frequencies and the other was a smaller-valued capacitor (with a lower equivalent series inductance: the decoupling capacitor) to filter the higher frequencies.
At that time, decoupling capacitors were widely regarded to be ineffective at frequencies above their self-resonant frequency (the frequency at which their self-capacitance resonated with their connection inductance). However, in due course it was shown that capacitors were generally effective well beyond their self resonant frequency and that their effectiveness at high frequencies depended entirely on their connection inductance. As the speed of digital circuits has continued to rise, the importance of understanding and controlling decoupling capacitor inductance has become even more important. Today, effective decoupling strategies have as much to do with achieving appropriate inductances as they do with providing appropriate capacitances.
Today's high-speed digital systems use low-impedance circuits, near fifty ohms, much lower than the impedance of free space (377 ohms). These circuits use tiny voltages, but HUGE currents. Therefore, the near-field energy surrounding a digital circuit exists mostly in the magnetic-field mode, not electric.
2 PCB Power Requirements
PCB power requirements can be considered in three categories
- Individual ICs have instantaneous requirements (e.g. their switching transient)
- The board as a whole has fluctuating short term needs
- The board has long term continuous power needs
The power needs of the board may be supplied in the short term by reservoir and decoupling capacitors. The continuous power needs are met by the power supply, which may be off the board and fed via lengthy cables
- Long supply cables will have significant impedance
- Short duration power impulses can cause voltage drops across the supply cable impedance
- A high reservoir capacitor will have high energy storage but has poor HF impedance. It supplies the transient current to the chip during switching and minimises power supply droop
- A decoupling capacitor is required in parallel with the reservoir to decouple HF noise to ground (typically 1nF-10nF, ceramic or polymer dielectric) Decoupling capacitors use lower values to get lower HF impedance
3 Grounding Techniques for PCBs
General
Due to their intrinsic reactance and resonances, tracks, wires, “star grounding” (where all the local grounds for each stage are connected together and a wire is run from that point to a single ground point on the chassis), area fills (areas of copper on the PCB surface), guard rings (a ‘shielding’ track that carries no current), etc., cannot provide an adequate reference for a PCB except at low frequencies (usually below 1MHz).
For example, the rule-of-thumb for the inductance of PCB tracks on their own or single wires, is 1nH/mm. This means that just 10mm of PCB track has an impedance of 6.3Ω at 100MHz, and 63 Ω at 1GHz. For this reason, only unbroken areas of metal conductor can provide an adequate ground reference up to 1GHz (and beyond), due to the increase in inductive reactance with frequency.
In a PCB these are usually called power, ground, reference or 0V planes. Reference plane techniques allow dramatic reductions in all unwanted EM coupling when used in conjunction with the other techniques described here. Reference planes are also essential for almost every other PCB EMC design technique.
High-Frequency Ground
This is extremely important for high frequency interconnects
- at low frequencies, currents find the path of least resistance
- at high frequencies, currents follow the path of least inductance
This occurs due to the return current following the path of the outward current in the conductor through the ground plane. The main objective of a grounding pattern is thus to minimise the ground impedance and the size of any potential ground loops from a circuit back to the power supply. This is illustrated in Figure 1.
Figure 1: Ground Loops
Note that the approach is not to simply minimise the resistance at the frequencies of interest for EMC; it is the inductive reactance that usually dominates the eventual impedance characteristic.
Creating Reference Planes
A high-quality high-frequency reference must have a vanishingly small partial inductance and can be created on a PCB by devoting one (or more) layer(s) to an unbroken copper sheet. A 0V reference plane would be used as the 0V (or “ground”) connection for all its associated circuits, so that all 0V return currents flow in the plane and not in tracks. Power planes are created and used in a similar manner for power connections and their return currents.
0V reference planes must lie under all their components and all their associated tracks, and extend a significant distance way beyond them. Perforations such as leads, pins, and via holes increase the inductance of a plane, making it less effective at higher frequencies. “Buried via” techniques can be used to allow interconnections between tracking layers without perforating the reference plane.
For less demanding products a rule-of-thumb is that any gaps must have dimensions of 0.01 or less at the maximum frequency concerned. For a good plane at 1GHz, this rule implies that plane gaps should have dimensions of 1.5mm (remembering that the velocity of propagation in FR4 is approx. half of what it is in air). "Sneaking" tracks into a plane layer is not allowed.
Unavoidable gaps in a plane must not merge to create larger ones. PCB design rules should size clearance holes so that for regular hole spacings such as DIL packages, the plane "webs" between holes as shown by Figure 2.
Figure 2: Webbed 0V Plane under a Leaded IC
It is best to make reference planes rectangular (but not thin) to minimise their partial inductance and also to make the fitting of PCB level shielding easier.
Where there are a number of different power supplies, there may need to be a number of different power planes. Segregation of circuit areas makes it easier to fit several broadly rectangular power planes on the same layer. This is illustrated in Figure 3 and 4.
Figure 3: Segmentation of Circuit by Function
Figure 4: Multiple Power Planes
Multilayer PCB Stackup
PCB stack-up design is important in containing the electromagnetic fields while also providing for additional bypassing and decoupling of the power bus and minimising bus voltage transients. Some of the benefits of multi-layer PC board design with power planes are:
(a) The power planes, if properly designed, will provide an image plane effect. Since the return currents in the power planes are equal and opposite polarity to the associated signal currents, their electromagnetic fields will tend to cancel. Power planes can also reduce the loop areas of signal and power traces, resulting in a decrease of EMI emissions and susceptibility.
(b) A ground plane can lower the overall ground impedance, thus reducing high frequency ground bounce (i.e. the deviation of the ground plane from its zero volt reference level). Also, the impedance between the ground and voltage planes is lowered at the high frequencies and this reduces power bus ringing. EMC problems with single and double sided PCBs can often be alleviated by moving to multilayer
PCB Capacitor
On a multi-layer board, a PCB capacitor is created by the thin laminate separating the power and ground planes. On a single-layer board, this capacitive effect is also achieved by running the power and ground traces in parallel.
The advantages of the PCB capacitor are that it has a very high frequency response and low series inductance that is evenly distributed along the plane or trace. In effect, it is an evenly distributed decoupling capacitor on the whole board. No single discrete component has these characteristics. Such an arrangement is shown in Figure 5.
Figure 5: PCB Capacitor
Figure
Implementing Multilayer Stackup
1. Plan ground and supply planes first.
2. Place power planes next to ground planes to get best decoupling.
3. Reduce separation between ground and power planes to increase capacitance between planes. The smaller the distance between power and ground layer, the lower the impedance of the power supply becomes. This is the basic requirement for the voltage supply stability.
4. Do not sacrifice a ground plane to signal tracking unless the situation is critical.
5. Do not overlap power planes unless a ground plane separates the power planes. Overlaps can couple noise between the supply planes.
6. Use the shielding effects of supply planes to reduce electromagnetic emission: having more than four layers permits the design a signal layer for critical traces between two continuous layers (see Figure 5).
7. Minimise ground path impedances: shorter length, greater breadth and less return loop area gives less inductance.
8. Consider how EMI may use ground paths to flow into, and out of, a system (covered in detail in Unit 7 of this module)
Figure 6: Suggested Layer Stacks
4 The Capacitor at High Frequencies
Geometry and Capacitor Equation
The ratio of Q to Vo depends on the geometrical arrangement of the conductors and on the electrical characteristics of the dielectric i.e.
The capacitance of a parallel plate capacitor as illustrated in Figure 7 is:
Where A is the overlap area of the plates area in m2 and d is the separation between plates. This formula is accurate only when d is small in comparison with A.
Figure 7: Parallel Plate Capacitor
Permittivity
The permittivity is usually expressed as the product of a relative permittivity εr and the permittivity of free space εo
ε = εr εo
where:
εo = 8.854 x 10-12 F/m
The relative permittivity is unity for a vacuum and typically in the range of 2 to 6 for most dielectrics.
Capacitor Parasitics
Figure 8 shows the equivalent HF circuit of a capacitor: Besides the pure capacitance there is an Equivalent Series Inductance (ESL) and an Equivalent Series Resistance (ESR).
Figure 8: Equivalent Circuit of a Capacitor
(Note that typically ESR = 0 - 10Ω; ESL = 2 -20nH). A capacitor shows capacitive behaviour in the lower frequency range (i.e. the impedance decreases with frequency); for frequencies higher than the series resonant frequency the behaviour becomes inductive. Optimum decoupling is effected at the series resonant frequency. This is illustrated in Figure 9, with the series resonant frequency shown at 100 MHz.
Figure 9: Capacitor Impedance Characteristics
5 Practical Decoupling and Bypassing
General
Searching technical literature for information on printed circuit board decoupling tends to produce conflicting advice.
Papers have been published suggesting that capacitors should always be located near the active devices they are meant to decouple. Other papers indicate that capacitor location is not critical. Some advise that decoupling capacitors should be connected through short traces directly to the active device. Others advise that traces should never be used with decoupling capacitors. With little effort, it is possible to find conflicting advice related to capacitor values, capacitor loss, capacitor mounting and many other aspects of good printed circuit board decoupling strategies.
A primary reason for the discrepancies in the literature is that printed circuit boards are used in a wide variety of applications that have different design goals. The best power distribution strategy for a 50-layer all-digital board with a thousand interconnections will not be the best strategy for a single-layer, high-volume, mixed-signal board. Both boards may be state-of-the-art, high-frequency designs; but the constraints on the power distribution will be very different.
· Decoupling
o The art and practice of breaking coupling between portions of systems and circuits to ensure proper operation.
· Bypassing
o The practice of adding a low-impedance path to shunt transient energy to ground at the source.
A ‘classic’ arrangement of reservoir and decoupling capacitors on a simple PCB is shown in Figure 10
Figure 10: Classic Arrangement on Double-Sided PCB
Capacitor Types
Selecting the right capacitor is not easy due to their many types and behavioural performance. Nonetheless, the capacitor is one component that can solve many EMC problems. The following sections describe the most common types, their characteristics and uses. Surface mount capacitors are always preferred over leaded types because of their low parasitic elements.
Aluminium electrolytic capacitors are usually constructed by winding metal foils spirally between a thin layer of dielectric, which gives high capacitance per unit volume but increases internal inductance of the part.
Tantalum capacitors are made from a block of the dielectric with direct plate and pin connections, which gives a lower internal inductance than aluminium electrolytic capacitors.
Ceramic capacitors are constructed of multiple parallel metal plates within a ceramic dielectric. The dominant parasitic is the inductance of the plate structure and this usually dominates the impedance for most types in the lower MHz region.
The difference in frequency response of different dielectric materials mean one type of capacitor is more suited to one application than another. Aluminium and tantalum electrolytic types dominate at the low frequency end, mainly in reservoir and low frequency filtering applications. In the mid-frequency range (from kHz to MHz) the ceramic capacitor dominates, for decoupling and higher frequency filters. Special low-loss (usually higher cost) ceramic and mica capacitors are available for very high frequency applications and microwave circuits.
For best EMC performance, it is important to have a low ESR (equivalent series resistance) value as this provides a higher attenuation to signals, especially frequencies close to the self-resonant frequency of the capacitor in use.
Bypass Capacitors
High-speed switching environments generate noise on power lines (or planes) due to the charging and discharging of internal and external capacitors of an integrated circuit. The instantaneous current generated with the rising and falling edges of the outputs causes the power line (or plane) to ring.
This behaviour can violate the VCC recommended operating conditions or generate false signals, creating serious problems. A simple and easy solution must be considered to prevent such a problem from occurring. This solution is the bypass capacitor.
A bypass capacitor stores an electrical charge that is released to the power line whenever a transient voltage spike occurs. It provides a low-impedance supply, thereby minimizing the noise generated by the switching outputs of the device.
Usually, the aluminium or tantalum capacitor is a good choice for bypass capacitors, its value dependant on the transient current demand on the PCB, but it is usually in the range of 10 to 470µF. Larger values are required on PCBs with a large number of integrated circuits, fast switching circuits, and PSUs having long leads to the PCB.
A simple bypass circuit is shown in Figure 11, with a more complex high-speed arrangement depicted in Figure 12.
Figure11: Simple Bypass Arrangement
Figure 12: High-Speed Bypass
Decoupling Capacitors
General
During active device switching, the high frequency switching noise created is distributed along the power supply lines.
The main function of the decoupling capacitor is to provide a localised source of DC power for the active devices, thus reducing the switching noise propagating across the board and decoupling the noise to ground.
Ceramic capacitors are usually selected for decoupling; choosing a value depends on the rise and fall times of the fastest signal. For example, with a 33MHz clock frequency, a 4.7nF to 100nF capacitor would be suitable; with a 100MHz clock frequency, a 10nF would be preferred.
Apart from the capacitive value when choosing the decoupling capacitor, the low ESR of the capacitor also affects its decoupling capabilities. For decoupling, it is preferable to choose capacitors with an ESR value below 1.
Ideally, the bypass and decoupling capacitors should be placed as close as possible to the power supply inlet to help filter high frequency noise. The value of the decoupling capacitor is approximately 1/100 to 1/1000 of the bypass capacitor. However, as designs have progressively increased in both complexity and speed, this argument has become too simplistic.
Achieving good decoupling above 10MHz gets more difficult as frequency increases, because the inductance of component leads, PCB tracks, via holes, and capacitor self-inductance, inevitably limit their performance. The achievement of good power supply decoupling at higher frequencies using capacitors mounted close to IC power pins is discussed next.
Decoupling is therefore not just the process of placing a capacitor adjacent to the IC to supply the transient switching current; rather it is the process of placing an L-C network adjacent to the IC to supply the transient switching current.
The inductance comes from the capacitor itself (typically 1-2 nH for a SMT capacitor), the interconnecting traces (typically 5 to 20 nH according to the layout) and the lead frame of the IC (typically 4 to 15 nH according to the type of IC package).
It is this inductance that limits the effectiveness of the decoupling network. It is very important to remember that an L-C network is being placed between the power and ground, not a capacitor!
< 50 MHz
Under 50 MHz (and recalling earlier discussion on the harmonics of the clock) traditional decoupling methods are effective. Using one or two decoupling capacitors (often 0.1 or 0.01 uF) placed close to the IC power and ground pins. Consider the loop area formed between the decoupling capacitor and the IC and place the capacitor for minimum loop area.
50 to 500 MHz
Above 50 MHz discrete decoupling capacitors become very inefficient in providing effective decoupling. At these frequencies some form of distributed decoupling capacitance is necessary. This can be achieved by using many small capacitors spread out around the IC, or by taking advantage of the distributed interplane capacitance (PCB capacitance as discussed previously) between the power and ground planes.
The key to using multiple capacitors for high frequency decoupling is:
(1) Make them all the same value
(2) Spread them out around the IC -- do not place them together.
The reason that this works is that when equal value L-C networks are placed in parallel, the total capacitance is equal to NxC and the total inductance is L/N where N is the number of capacitors used.
In other words, for parallel L-C networks the capacitance value multiples up by the number of networks used and the inductance value divides down by the number of networks used. Both of these effects are valuable.
For a fixed value of inductance, the effectiveness of the high frequency decoupling network is, therefore, solely dependent on the number of capacitors that are used. The more capacitors, the lower the total inductance and the better the high frequency decoupling.
Intel, as an example, recommends 41 decoupling capacitors in order to effectively decouple a Pentium®-microprocessor (Intel Application Note AP-579). When a large number of capacitors are used, their exact placement becomes less important than when only one or two capacitors are used.
Conversely, the problem with using multiple capacitors of different values is that the different value capacitors produce an anti-resonance, or cross-resonance (which produces an impedance peak). .
Although the effectiveness of the decoupling at high frequency is dependent on the number of capacitors used (since the inductance is reduced to L/N), the effectiveness of the decoupling at low frequency has nothing to do with the number of capacitors used. The low frequency decoupling effectiveness is solely dependent upon the product value of capacitance (CxN). The larger the value of this product, the lower the frequency that the decoupling is effective.
If the calculations are performed, it will be found that
even with multiple discrete decoupling capacitors, regardless of how many are used
or where they are placed, the technique is only effective up to about 500 MHz.
500 MHz to 5 GHz
Embedded PCB Capacitance: The limit to the concept of the use of a large number of discrete decoupling capacitors is the use of distributed decoupling capacitance, by taking advantage of the distributed interplane capacitance between the power and ground planes of the PCB.
This amounts to an infinite number of infinitesimal capacitors. The only effective means to achieve effective decoupling above 500 MHz is to use some form of distributed interplane capacitance (this technique is also effective down to about 50 MHz). To be effective above 50 MHz a power-ground plane capacitance of about 1000 pF/sq. in. is required. Standard layer spacing of 5- to 10-mils provides capacitance that is 1/5 to 1/10 of this required amount.
In 1989-1990 Zycon developed a special PCB laminate with a 2-mil spacing between layers using standard FR-4 epoxy glass as the dielectric. This laminate (known as ZBC-2000μ) provides 500 pF/ sq. in. of interplane capacitance. By using two sets of power and ground planes in a PCB, the desired 1000 pF/sq. in can be achieved. Zycon refers to this technology as Buried Capacitance. It is now available from a variety of manufacturers.
A time-domain view of ‘good’ power supply decoupling in shown in Figure 13. Note that the short-term power demand is supplied by the PCB capacitance.
Figure 13: Effective Power Supply Decoupling
6 Decoupling Design
There are essentially three basic approaches that are commonly used to determine how much decoupling capacitance is necessary for a given board design. These approaches are now described in some detail.
Simple Guidelines
Despite the importance of providing adequate printed circuit board decoupling, most board designers use very simple design guidelines to determine how much bulk and local decoupling to use.
Generally these design guidelines are based on past experience with other board designs or component application notes that may or may not be relevant to a particular board design. These guidelines rarely take into account parameters such as current drawn by the components, allowable noise voltages or the board stack-up.
Instead, a guideline is likely to read something like, “…include one 0.01 mF local decoupling capacitor for each Vcc pin of every active component on the board plus 1 bulk decoupling capacitor with a value equal to 5 times the sum of the local decoupling capacitance.”
Simple guidelines such as this may work well for one particular application, while being totally inappropriate for others. Without accounting for the power requirements of the circuit design in question or recognising that the location and mounting inductance will affect the amount of decoupling required, it is unlikely that optimum decoupling will be achieved based on this type of design guideline.
Maximum Impedance Approach
A more systematic approach to printed circuit board decoupling is to determine the maximum allowable impedance that the power distribution network is allowed to have and then choose the decoupling capacitance to meet this goal.
The maximum allowable impedance is generally determined by dividing the maximum allowable power bus noise voltage by the maximum current drawn by the active device(s) being decoupled. For example, if a particular component can draw as much as 2 amps of current and the power bus noise voltage must be kept below 300 mV, then the maximum power bus impedance would be:
It should be noted that a given decoupling capacitor will have an impedance that decreases with increasing frequency (at lower frequencies) and then increases at higher frequencies where its connection inductance dominates (see Figure 3).
Decoupling capacitors thus are chosen to ensure that there is enough capacitance to provide adequately low impedance at the low frequencies and that they are connected with a low enough inductance to meet the high-frequency impedance requirements.
Capacitance Ratio Approach
A significant drawback of the maximum impedance approach is that the current requirements of the board as a function of frequency are not usually provided or easy to determine.
Typically, the peak currents used to determine Zmax are calculated in the time domain. This can result in over-designed boards, however, since the current requirements in one frequency band may be quite different than the current requirements in another.
The capacitance ratio approach avoids a direct calculation of the board currents, by recognising that CMOS circuits draw currents proportional to device capacitances on the board.
Consider the circuit in Figure 14, which consists of two capacitors and a switch connected in series. The capacitor on the right, CL, represents a CMOS load capacitance that will draw current from the power bus when it is charged. The capacitor on the left, CD, represents a decoupling capacitor attempting to maintain a constant voltage on the power bus. At time t=0, the switch closes charging CL and causing the power bus voltage to decrease slightly. A higher ratio of CD to CL, results in a smaller change in the power bus voltage.
Figure 14: Capacitor Ratio Effect
If Vi is where Vi is the initial voltage across CD and Vf is the final voltage across CL and CD, it can be shown that:
Where ΔV is the change in voltage Vi – Vf. This equation suggests that total decoupling capacitance should be set to a value that is equal to the total device capacitance times the power bus voltage divided by the maximum power bus noise.
For example, consider a board with one device that drives 32 CMOS loads (5 pF per load) and has a power dissipation capacitance, CPD, of 380 pF. If the power bus voltage is 3.3 volts (Vi) and the maximum allowable power bus noise voltage is 300 mV (ΔV), then the amount of decoupling capacitance required for this board is:
= 6nF
Since this approach does not account for the inductance of the capacitor connections, it is up to the designer to ensure that the capacitance is available to the device at all of the frequencies of interest. One method of doing this is to give each mounted decoupling capacitor an effective capacitance value that is its nominal value minus a term related to its connection inductance and frequency or transition time.
7 Summary
The importance of good grounding techniques for PCBs cannot be over-emphasised: for modern high-frequency designs this invariably means the use of power and ground planes. These should be continuous and uninterrupted to minimise inductance.
Power bus decoupling is an important part of any printed circuit board design. Strategies for effective decoupling depend on many factors including the board layout, board stackup, current requirements of the active devices and power bus noise requirements. Three general approaches have been described depending on whether or not the board has power planes and how closely these planes are spaced. Minimising connection inductance is an important aspect of all three approaches.
While the three approaches described will help to determine the best way to locate and mount decoupling capacitors, they do not address the issue of how much decoupling is enough for a given application. Two methods were described for answering the question, “How much is enough?” While neither method is likely to give you an exact answer to this question, either method is preferable to relying on luck or rules-of-thumb based on experiences with older-technology products. A proactive, informed strategy for power bus decoupling, is much more likely to result in an effective board design that meets or exceeds all of its requirements.
Good bypass and decoupling design plays a critical role in the control of power and ground noise, crosstalk and electromagnetic radiation.