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Printed Circuit Design

Unit 3: Packaging and Assembly

Contents

• 1 Introduction
• 2 Mass Soldering Techniques
  • 2.1 Environmental Issues
  • 2.2   Solder Alloys
  • 2.3 Wave Soldering
  • 2.4 Re-flow Soldering
• 3 Electronic Component Packaging
  • 3.1 Through Hole Mounting
  • 3.2 Surface Mount Packaging
  • 3.4 TAB (Tape Automated Bonding)
  • 3.5 BGA (Ball Grid Array)
  • 3.6 PCB Issues
• 4 Land Pattern Design Standard (IPC 7351 A)
  • 4.1 Land Pattern Naming Convention
  • 4.2 Land Pattern Syntax Naming Explanations
  • 4.3 Land Pattern Sizing and Type
  • 4.4 Placement Courtyard
  • 4.4 Other features of IPC 7351A
  • 4.5 Land Pattern Software
• 5 Summary

1 Introduction

The following unit concerns the use of the PCB in the assembly of the completed electronic product.  The issues which are involved with the reliable and repeatable manufacture of an electronic system will be considered here.  There are points which the PCB designer must be aware of to ensure that the final product can be manufactured.

The RoHS (Restriction of Hazardous Substances) directive is forcing manufacturers to use lead-free solders to manufacture a wide variety of electrical equipment. All lead-free solders are “different” to tin/lead solder but as yet there are no clear guidelines or standards for lead-free solder circuit design. Design engineers searching for publications recommending designs for pads, tracks and board layout specifically for lead-free will find very little information.

Many manufacturers who have already re-designed their products for lead-free processes have found that changes to circuit design do not need to change, but this is not always the case, especially with more complex PCBs.

The impact of lead free solder is one which despite being soon due for full implementation must be considered in respect to the design of the PCB to meet the requirements of lead free legislation.  There are several situations where lead-free solders might influence circuit design.

The issues which will be covered will be a brief overview of the methods of mass soldering, wave soldering and reflow soldering.  Any issues which must be considered by the PCB designer will be introduced and considered.

The types and forms of the most common packages used will be covered and issues discussed.

The design of land patterns (or pads) is something which is largely overlooked.  The correct sizing of a land pattern has considerable impact on the finished product.  There are several standards which should be used to produce a land pattern which meets the needs of each application.  The standard will be reviewed and the issues discussed.

2 Mass Soldering Techniques

Soldering is the joining together of two metals to give physical bonding and good electrical conductivity. It is used primarily in electrical and electronic circuitry. Solder is a combination of metals, which are solid at normal room temperatures and become liquid at between 180 and 240°C. Solder bonds well to various metals, and extremely well to copper.

For soldering to take place, the alloy has to 'wet' the surfaces to be joined; 'wetting' means that the solder metallurgically interacts with the substrates, thus forming a strong bond on solidifying. Fluxes are an important part of the whole process, since they ensure that all the surfaces are clean and oxide-free, thus promoting good wetting. Wetting is a term that describes good adhesion of the solder to the components being soldered. Tin is an important constituent of the majority of solders because of its ability to bond with a large number of metals

Soldering traditionally has been the most economical and reliable method of joining that are attached to PCBs. Automated soldering equipment for wave or planar (drag) soldering components can be easily and economically installed. A quality end product results from the high reliability achieved by mass soldering. Soldering offers the additional benefit of providing for sequential assembly, a common practice in the electronics industry.

2.1 Environmental Issues

2.1.1 Lead-Free Solders

Lead is widely used in traditional solder alloys, but environmental concerns mean this is unlikely to continue. The toxic nature of lead on all forms of life is well understood, and with landfill sites containing more old electronics, the polluting potential is clear. Both the automotive and telecomm industries have medium term plans to remove lead from their products.

The suggested alternatives are based on 99% Tin and have a melting point of between 200 and 240ºC, depending upon the alloying metal used. To replace the excellent soldering performance provided by Tin Lead alloys is proving difficult and a large body of research is underway involving the use of silver, copper and other more exotic metals.

Among thermal, mechanical, creep, fatigue, and other properties, melting point is one of the most important. Table 1 provides a select list of lead free solders that have been available for some time.

Table 1. Examples of some lead-free solders and their properties

It should be noted that the compositions of the lead-free solders are still being optimised to achieve the desired properties. So the compositions of the solders shown in Table 1 may vary slightly from commercially available solders at different points in time.

.From Table 1, we can see that the lead-free solders have either much lower melting points or much higher melting points than tin-lead eutectic solder, which has a melting point of 183°C 183 ^oC.

Special flux is necessary when low temperature solders are used, because the standard flux may not be active at lower temperatures. Another problem associated with low temperature solders is the reduction in wetting properties caused by the lower fluidity at sub-eutectic temperatures.

Many other alloys shown in Table 1 have much higher melting points than tin-lead eutectic. For example, zinc-tin, a high temperature lead-free solder has a melting point of 198°C.

The high melting point solders will be incompatible with widely used board materials such as FR-4. In addition, higher temperatures necessary for rework can significantly increase the potential for board damage.

In general, almost all of the lead-free solders exhibit less wetting (spreading) than tin-lead eutectic and this causes an inferior solder fillet. To improve the wetting properties, special flux formulations are required. The fatigue properties of lead-free solders are also not as good, although in one study no degradation of solder joint integrity was observed after thermal cycling with high temperature 96.5 Sn/3.5 Ag (the last alloy in Table 1.

Higher surface tension means an increased risk of tomb-stoning [1] (where a component stands ‘on-end’ with only one connection made) and bridging [2]. The techniques used avoid this defect with tin/lead solders are even more important with lead-free solders.

2.1.2  Developments in Fluxes

Fluxes are used in soldering to corrosively clean the joint area and to aid the transfer of heat from tip to joint. They are rated in terms of their activity, with an aggressive acidic flux said to be highly active.

The most commonly used flux compositions are based on the naturally occurring substance, Rosin. RMA (Rosin Mildly Activated) flux is the most common. Unfortunately rosin contains colophony, which has significant health and safety implications. When heated to soldering temperatures colophony will liberate fumes that are classed as irritants. A fume extraction system, of high specification, must therefore be provided for users.

It is inevitable that a residue will be left on the joint after soldering. If the flux is very active, i.e. the organic water soluble or inorganic acid varieties, then residue the must be removed to prevent corrosion from compromising the joint over time. Most industrial users also choose to clean RMA residues for process reasons, the most efficient medium being CFC solvents. The phasing out of such solvents because of the environmental damage that results from their use, was a difficult challenge to the electronics industry.

The response was the development of no-clean flux. They differ considerably from RMA fluxes in their composition. The chemical activity of the solids used are not less than those found in an RMA, they just contain less by volume (typically 1% as opposed to 10%). This situation is a good example of compromise between features, activity is lowered to remove the need for cleaning, but this reduces the flux efficiency.

2.2   Solder Alloys

As has been shown above a wide range of solder alloys are available to suit the various requirements. In the electronics industry, a sharp melting point at not too high a temperature is desirable, in order to avoid thermal damage to components.

One of the most important characteristics of a solder alloy is its melting point. The actual value is relevant, but more important is the range of transition from liquid to solid. Where this is narrow (less than 1ºC) the chances of producing a "dry" joint are minimised.

Solders are predominantly alloys of tin, which has a melting point of 232 ºC. Other metals are added to produce the desired physical characteristics at an economic cost, and to achieve a specific melting point. Every alloy has a proportional mix where the rapid transition described above exists. This is known as the eutectic point (from the Greek "well meltable") and an alloy of 62% tin and 38% lead exhibits this property at 183ºC. Figure 1 shows a phase diagram for this alloy.

Figure 1:  Phase Diagram for Solder/Tin alloy (similar diagrams exist for lead free materials)

 

Solder pastes comprise a very fine alloy powder dispersed in a viscous flux medium, and function like a versatile type of preform: pastes can be deposited in virtually any required shape or thickness by a number of methods, and they are subsequently heated or `reflowed' to make the joint.

The fluxes required for the soldering process may be applied in a separate stage, but they are often intimately mixed with the solder itself.

2.3 Wave Soldering

For maximum output and efficiency, various mass soldering techniques have been devised that are able to produce a large number of soldered joints in a short time. One of the earliest of these processes is called wave soldering.  It employs a continuously generated wave of molten solder to form the joints. A printed circuit board with all its components in position is placed on a gently inclined conveyor, which carries it through each of the soldering stages.

One of the advantages of wave soldering is that the process is easily automated with the use of a conveyor system to move the boards. Conveyor systems can move boards on flat pallets or by the use of finger conveyors. In either case, the conveyor system is constructed of a material that does not bond with solder. The conveyor moves the board into the fluxing area, from the fluxing area through a preheating process, and then over the solder wave. 

Each stage will now be considered in the order that a board would be passed through.  First the flux is applied.  Second, the board is then heated for three reasons; i) to dry out the solvent within the flux ii) to active the flux and iii) to induce heat into the plated through holes, board and components to reduce the temperature shock of the hot colder.  Thirdly the board is passed through the solder wave.

2. 3.1 Applying Flux

The first stage is fluxing, where the underside of the circuit board (i.e. where the intended joints are located) passes over a fluxing device. The flux is always applied in liquid form in order to cover all the flux areas quickly and evenly.  The board then passes over heating panels that evaporate the flux solvent on the board, activate the flux itself, and preheat the board to minimise thermal shock.

Flux can be applied in a number of ways but the most common way of applying flux in a wave soldering process is foam fluxing. The flux is aerated with extremely fine bubbles of compressed gasses, causing it to foam up. The printed circuit board then moves across the top of the foam head, picking us some of the flux. An air knife is then used to help remove the excess foam as the board exits.  The picture below illustrates this.

Figure 2: Flux Wave Machine

 

There is an optimum range for the amount of flux that is retained on the board to ensure satisfactory soldering and the attainment of this optimum depends on two factors:

1. the method of application and hence the quantity of liquid applied;
2. the fraction of solvent to flux solute and hence its viscosity and its evaporation behaviour between application and soldering.

2.3.2  Preheating

During preheating the printed circuit board, with its components, is heated in order to raise the base metals to their soldering temperature. If these metals are already at or near the required temperature when the solder is introduced, the amount of time that the solder, in its liquid form, must be in contact with the board is minimized. This results in a much stronger inter-metallic layer. Heating the board up at a slow steady rate also works to minimize thermal shock to the board and its components. Simply subjecting a room temperature circuit board to a wave of liquid solder without any preheating can cause extensive warping and cracking.

The amount of heat required during the preheat stage depends on the board design and its component materials, but more importantly on the properties of the flux being used.  If the preheating is too low the viscosity of the flux will be too low and at the solder wave it may be prematurely washed from the board, giving rise to poor wetting of the solderable surfaces.  Additionally if this happens the flux will not be present at the exit meniscus increasing the likelihood of solder ‘bridges’ and ‘icicles’.  The heating of the flux besides drying out the liquid it is dissolved in also initiates the breakdown of the oxide surfaces of the layer to be soldered.  If there is too much preheating the viscosity will rise and it will not be adequately melted prior to the solder wave which cannot then be pushed aside by the molten solder.

2.3.4 Soldering

The circuit board finally passes over the solder wave, which contacts the whole underside and forms all the desired joints.

Liquid solder is pumped up through a nozzle and out the end. Gravity then causes the solder to fall back down; creating a parabola shaped "wave." The printed circuit board, with the electronic components already inserted, travels over the apex of the wave. As the wave of solder comes in contact with the bottom side of the board, the already fluxed metals chemically bond with the solder.

The diagram below illustrates the principles of most modern wave solder machines, where TWO waves are used to complete the process.

Figure 3: Dual Wave Solder Principles

 

The first wave is a turbulent wave and the second smooth.  The first wave drives molten solder between the components and ensures all terminations are heated and have achieved full wetting, before contact with the smooth second wave which then controls the meniscus of the solder at each joint, as the board leaves the calmer wave at near zero velocity.

2.3.5 PCB Issues

A problem which is normally encountered in wave soldering of SMDs , particularly packages like SOIC, is bridging of leads. Sometimes it is necessary to shorten the protruding solder land, and reduce the conveyor speed, or to use solder thieves. When SOIC packages are positioned with their long axis parallel to the transport direction, bridges tend to occur at the trailing end between the penultimate and last leads. The solution is to add a fake solder land downstream, usually called a solder thief.  These oversized pad areas, help to attract any excess solder not pulled into the standard joint formations, thus reducing instances of bridging.

This is an issue which is particularly problematic with lead free soldering as the higher surface tension of lead free solders and the reduced spacing of surface mount components both accentuate this difficulty. 

The diagram below illustrates how the direction of travel through the board determines the positioning of the solder thief.  There are two methods commonly used, the first adds an extension to the last pad and the second uses a completely separate pad.

Figure 4:  Examples of the addition of ‘solder thieves’ to pads

There are several other suggestions which should be considered. If possible Increase spacing between pads to minimise risk from bridging.  Try to align multi-pin components parallel to solder transport direction.   As wetting is inferior, use smaller pads to ensure that no pad areas remain without solder. This will be important for equipment used in corrosive environments. “Rounding” of corners of pads helps prevent thermal decomposition of flux at higher lead-free temperatures.

Figure 5: Flux Change of Pad shape to improve wetting

 

One of the key problems in using the higher melting point lead free solders in wave soldering is that they increase the potential for capacitor cracking. The wave soldering temperature needs to be kept at about 230°- 245°C, which is about 45°- 65°C above the melting point of tin-lead solder. A lead-free solder with a melting point of 220°C will require 265°- 280°C wave temperature. This increases the delta temperature between the preheat and the wave and hence the potential for capacitor cracking.

2.4 Re-flow Soldering

In the other main technique called reflow soldering, the solid solder is placed in its correct position first, and then heat is subsequently applied by some means to melt it and form the joints.

The solder can be in the form of paste. Solder paste can be applied to a circuit board by syringe, stencilling, or screen printing, and these techniques are capable of very great accuracy. This is important where components are mounted directly onto the surface of a board, instead of their leads being inserted through drilled holes; surface mounting enables components to be packed more closely together, and thus accurate printing of solder paste is essential.

There are various ways to apply heat in a reflow process. These include convection (hot gas), infra-red and vapour phase. Heating by means of a hot belt is suitable for smaller circuits, while a more recent technique for specialised applications uses a laser beam to heat each joint in turn.

Surface mount components can be wave soldered, they must first be attached to the circuit board with some type of adhesive or cement in order to keep them in place during soldering. This introduces another step in the assembly process. Since the whole surface-mount component is immersed in the wave, it must be constructed in such a manner to withstand the high temperature of the liquid solder.

In a reflow process, solder paste is put on the component sites of the printed circuit board, and then the components are put on the board on top of the solder paste. Often a separate adhesive is used to hold the device in place until soldering takes place. The board and attached components are then heated to activate the flux, elevate the temperature of the base metals, and melt (or "re-flow") the solder.

2.4.1 Solder Paste Printing

Screen printing is the most common way of dispensing the solder paste onto the circuit board. This is essentially the same process that is used in applying paint to clothing and street signs. A screen stencil is placed slightly above the board, and a squeegee is manually drawn over the stencil, forcing solder paste through the screen onto the board. The amount of solder deposited can be quite accurately controlled with the density of the screen and the shape of the squeegee. The alignment between the board and screen is very important. If the either of them move even slightly, or if the alignment is even slightly off, the solder will not be deposited in the right place.

2.4.2 Heating

The assembly, the board and its components with solder sandwiched between, is uniformly heated to a predetermined temperature. It is then held at this temperature to give the solvents in the solder paste time to evaporate and dry. This is the same temperature that the flux becomes active, and begins to clean the base metals. After a sufficient time at this temperature, the temperature is raised above the melting point of the solder and held for a time, usually between thirty and sixty seconds. The board is then slowly cooled at a continuous rate. There is a trade off here; cooling the board quickly results in a very strong solder bond, but it also introduces stresses into the board.

A common type of convection heating is vapour phase heating. A liquid is boiled, causing some of it to vaporize and saturate the air within the vapour chamber. When the board is inserted into the chamber, the vapour condenses onto it. Energy is transferred from the vapour to the board during condensation, causing the board to heat up. The temperature that the board is heated to is the boiling point of the liquid. The fact that this is a very fast heating method and that the increase in temperature is very uniform makes it advantageous. Another advantage of this method is that it is performed in a closed vapour chamber where no oxygen is present. When oxygen is not present during the heating process, oxidation does not occur. This allows the use of a very mild flux in the solder paste. Sometimes the flux that is used is so mild that cleaning is not required.

Radiation heating allows the assembly to be heated using electromagnetic waves. Just as in a household microwave, these waves do not heat up the air in-between their source and the board. Either infrared or laser light is used. These processes allow precise control of the amount and placement of the transferred energy. The drawback of these methods is the slow rates at which they heat up the boards.

2.4.3 PCB Design issues

There are no new formal standards for design of PCBs that use lead-free solders, but component manufacturers will include (in their technical datasheets) the dimensions of pads that they recommend for their components.  These should be used unless modifications as described above prove to be necessary or these problems are suspected from previous experience.

There are several other issues that should be considered.

PCB warping, using the higher reflow temperature required for lead-free increases warping of laminate. At high temperature, the laminate becomes soft in reflow ovens with conveyers that support the sides of panels only, these are likely to sag in the middle. This can cause some components to have poor solder bonds and to produce warped boards.

-Vias and plated through holes are stressed during reflow because the thermal coefficient of expansion of the laminate in the direction perpendicular to the board is greater than that of copper. This can cause cracks and open circuits, particularly if the hole drilling or plating are of poor quality. This risk increases with reflow temperature and is more likely with lead-free but can be reduced by using:

• Larger hole diameters
• Thinner laminate
• Avoid paste in hole connectors (use wave or hand soldering)

In most reflow ovens, the temperature at the sides is lower than at the centre. Therefore avoid locating large components at the edge and small heat sensitive components at the centre.

3 Electronic Component Packaging

The level of advancement and development in electronic component packaging is lagging behind the advances in microelectronics. This is due to the inherently multi-disciplinary field of electronic packaging, which incorporates several of the traditional sub-areas of mechanics, electronics, physics and chemistry. The most prominent of these areas are heat transfer, materials, signal transmission, mechanical analysis and manufacturing.

Most electronic applications require increased reliability and performance as well as lower cost, weight and size. All of these factors depend on the capabilities related to making more integrated components, which in turn depend on advanced assembly equipment that can put a large number of small components into smaller and smaller areas.

 A typical microelectronic package is designed to provide the following functions:

• Connections for signal lines leading onto and off the silicon chip.
• Connections for power lines that powers the circuits on the chip.
• Connections of signal lines between the system components and interconnections for input/output terminals.
• Removal of the heat generated by the circuits.
• Support and protection of the bare chip.

There are a large number of requirements that an electronic package has to fulfill, such as:

• Mechanical requirements: These may involve constraints on the structure and thermal characteristics of the supporting substrate. The substrate is a base material that provides a supporting surface for deposited or etched wiring patterns - for attachment of component parts, or for fabrication of a semiconductor device.
• Input/Output (I/O) requirements: These vary significantly depending on the system of interest. For example, the I/O ports for a hand-held calculator are the keyboard and the display. By contrast, in a large computer system the I/O ports may include tape drives, disk drives, printers, etc.
• Environmental requirements: Tolerance of the packaging to operating conditions such as air humidity and exposure to chemicals.
• Reliability requirements: The system's ability to operate for many years with very few problems.
• Interconnection requirements: The number of I/O ports that are needed to provide inter-chip communication, ie. between chips and the supporting substrate.

It is the size of the individual component packages, as has been mentioned earlier, which determines the final size of an electronic system.   The demand from consumers has been for smaller and more efficient products.  The industry has responded by putting more complex circuits in smaller packages with more connection points (pins) than was previously achievable.  The diagram below illustrates the growth in complexity of circuits in a single package.

Figure 6: Comparison of Device Complexity against Number of Device Pins for Different IC Packages

 

Each of these will now be considered. 

3.1 Through Hole Mounting

This method requires packages which have leads that rely on holes in a multilayer PCB for the purpose of mounting.  The extended leads are then soldered for permanent mounting.  Some of the packaging technologies which use this mounting method are:

• Dual In-line Package (DIP)

One of the earliest standards was the rectangular DIP. It still accounts for some 15% of all integrated circuit packaging, though this figure is reducing rapidly.  The DIP has I/O leads which extend from two opposite sides of the package and are bent downward.   With pins spaced 2.4 mm apart on only two sides of the package, the physical size of the DIP has become too great. On the other hand, the physical size of an unpackaged microelectronic circuit (bare die) has been reduced to a few millimeters,. As a result the DIP package has become up to 50 times larger than the bare die itself, thus defeating the objective of shrinking the size of the integrated circuits.

• Pin Grid Array Package (PGA)

Another type of packaging which requires through hole mounting is the pin grid array (PGA), which is typically used with VLSI chips that require pin counts greater than 100. The PGA is often composed of a square, multilayer, ceramic chip carrier with a matrix of butt-brazed through hole pins under its surface. The cost of pin grid array packages is much higher than that of DIPs, because PGAs are made of ceramic and are generally multilayer. However, the PGA provides up to a four fold improvement in pin density over the DIP, when tight array spacing is employed. A typical pitch spacing in this technology is in the order of 0.4 to 0.5 mm.

A sample diagram of a DIP package is shown below.

Figure 7: Mechanical Drawing of DIP package

 

Through-hole continues to be important for assemblies which contain:

• thermally sensitive components, such as batteries;
• components such as large connectors and sockets, whose mechanical configuration does not lend itself easily to surface mount solution.

Areas where the inherent mechanical strength of the crimped legs mean that the components are not likely to ‘fall off’ the board.  It is, however, becoming difficult to get some components in this type of package. 

3.2 Surface Mount Packaging

The rationale behind surface mounting was that putting wires into holes wastes space and such technology has an inherent lower limit on lead diameter and thus lead pitch. The idea of surface-mounting components had already been used for high-reliability military purposes in the form of flat-packs. Although still used in specialised applications, development was restricted by their high cost and the need to use gold-plated leads and solder components individually.

Various lower-cost alternatives were offered, of which the most successful was an encapsulated chip in a small outline with leads that could be easily soldered onto contact pads on the substrate. Many standard outlines for discrete semiconductors and integrated circuits have been made available since the SOT-23 was released in the late 1960’s. Yet these early components were unreliable and at first competed with the more direct use of chips, which generally produced a smaller overall circuit.

Circuit boards for SM assembly have specific requirements - both designer and manufacturer need to understand the requirements of the assembler and end-user:

Image definition. SM designs tend to have fine surface details with narrow spaces between tracks and pads. This requires excellent drill tooling and imaging systems and in particular a good solder resist registration system to prevent encroachment of the resist onto the pads whilst ensuring its covering of tracks and dielectric areas between pads and tracks.

This has encouraged a trend towards photo-imaged dry film solder resist or wet resist rather than screen printing of solder resist.

Surface flatness. SM components need to be seated flat on to the areas where soldering occurs and therefore the height of the pads and solder resist above the surface of the laminate must be within strict tolerances and even across the board. Sometimes components can actually rest on top of the solder resist!

Surface finish. Generally Hot-Air Solder Levelled (HASL), has been used to provide a thinner, flatter surface. Alternative materials used by other manufacturers include nickel-gold plating, or no plating at all, normally with a thin organic protective film.

Soldering    Whilst solder has made all electronic assembly possible, one aspect which slowed the progress of SMT was the questionable reliability of the joints. This is a complex function of:

The thermal expansion mismatch between the PCB and components, especially ceramic, can lead to stress-induced fatigue during temperature cycling, with micro-cracks in the solder and eventual open-circuits.

The effect of the process, component and pad geometry on the joint geometry and fillet shape.  Results in interactions between the solder and metallisation.

The solderability of many components used for reflow techniques, where there is negligible mechanical agitation to assist wetting, has also too often been marginal. Suppliers have been protected by the prolonged search for standard quantitative methods of solderability testing which truly reflect the reflow process.

The key to progress has been the realisation that the tolerance of SM joints to processing errors is limited and a greater degree of process control is necessary than for through-hold assemblies.

3.3.2 SOIC (Small Outline Integrated Circuits)

One of the earliest members of the surface-mounted family is the flat pack package. It is similar to the DIP with the exception that the leads protrude outward to form a flat surface and are mounted on pads, in order to obviate through hole-mounting. Flat packs are found in (i) a dual in-line pin configurations called small outline integrated circuits (SOIC) and (ii) a configuration with leads which protrude on all four sides of the component package. SOICs typically have gull wing-type leads and are preferred for lead counts of up to 20 pins. The pitch spacing in the SMT is in the order of 1 mm as opposed to 2.4 mm for DIPs.

The SOIC is about 35% the size of a DIP package.  A technical drawing of the SOIC package is shown below.

Figure 8: Mechanical Drawing of SOIC package

 

3.3 QFP (Quad Flat Pack)

Quad Flat Pack (TQFP) packages provide space-efficient packaging solution, resulting in smaller printed circuit board space requirements. Their reduced height and body dimensions are ideal for space-conscious applications, such as PCMCIA cards and networking devices.  TQFP solutions can provide up to a 75% reduction in printed circuit board space.

Figure 9: Mechanical Drawing of QFP package

 

3.4 TAB (Tape Automated Bonding)

Tape-automated bonding (TAB) is an approach to fine the pitch interconnection of a chip to a leadframe. The interconnections are patterned on a multilayer polymer tape. The tape is positioned above the `bare die' so that the metal tracks (on the polymer tape) correspond to the bonding sites on the die.  A new version of TAB, referred to as `area TAB', borrows a good idea from a bonding technique called `bump bonding'.  In this version, metal bumps are distributed over the entire surface of the chip (ie. I/O and power/ground terminals are not constrained to the chip periphery) - thus a large I/O count becomes viable.

Figure 10: Tape-automated bonded die with a bare chip placed on the tape and connected to an interconnection pattern

 

The tape-automated bonding technology provides several advantages over the wire bonding technology. These advantages include:

• a smaller bonding pad compared to wire bonding technology
• smaller on-chip bonding pitch in the range of 100 mm
• a decrease in the quantity of gold used for bonding
• the reduction of variations in bond geometry
• an increase in production rate because of area or `gang' bonding
• a stronger and more uniform inner lead bonding strength.

In addition to better electrical performance (noise and frequency), lower labour costs, higher I/O counts (up to 850 pins) and lighter weight, greater densities are achievable and the chip can be attached in a face-up or face-down configuration.

On the other hand, the disadvantages of TAB technology include the time and cost of designing and fabricating the tape and the capital expense of the TAB bonding equipment. In addition, each die must have its own tape patterned for its bonding configuration. For these reasons, TAB has typically been limited to high-volume production applications.

3.5 BGA (Ball Grid Array)

Peripherally leaded packages, such as quad flat packs (QFPs), are cost-effective vehicles for semiconductor devices until the pin count goes above 200. Area array interconnection schemes take over above 200 pinouts because they take less board area, often with a much more relaxed I/O pitch. Pin grid arrays (PGAs) have been used for advanced, large I/O devices, such as the 80486 processor, and they still are. But now, the ball grid array (BGA), the surface mount variety of area array packages, is the package of choice for these devices

BGAs come in a variety of configurations and material sets.. Most use the classic die bond and wire bond scheme for the first-level interconnect, while some of the more advanced devices are flip-chip attached. Package substrate materials vary to optimize cost, thermal management, moisture resistance and interconnect reliability at either the first (chip-to-substrate) level or second (package to board) level.

The BGA takes advantage of the previously unused under-chip real estate, increasing both the number of I/Os and the pitch, eliminating perimeter leads and reducing the handling problems associated with high pin-count devices. The best payoff is that current manufacturing methods and equipment can be employed, ensuring yields consistent with current standards.

The connecting balls are eutectic solder.  This allows for an easier one-step process during manufacturing, resulting in a more consumer-oriented product/price range of components. This interconnection technique results in components sitting much closer (about 0.020") to the PCB.

.

Figure 11: Mechanical Drawing for BGA package

 

3.6 PCB Issues

The temperature above which components distort or are permanently damaged depends mainly on the choice of materials within the part. Lead-free solders require a higher reflow temperature than tin/lead, a wide variety of components may be unsuitable for use unless component manufacturers have modified these parts to increase their maximum reflow temperature.  Most components are converted to comply with RoHS simply by changing tin/lead termination coatings to tin but changes to withstand the higher temperatures required are more difficult and often this is unchanged.

This has a significant impact on circuit design if the reflow temperature that has to be used for a particular PCB is higher than the maximum reflow temperature of a component, as this component cannot be used. If a substitute with the same function is not available from another manufacturer, then re-design will be necessary. There are two possible options here;

Redesign circuit so that heat sensitive components can be attached using selective soldering or hand soldering after all other components have been attached, These soldering techniques do not heat components to as high a temperature as SMT but require space around the component.

As a last resort, the heat sensitive component will have to be changed to a different type, which often requires significant circuit design changes. SMT electrolytic capacitors are examples of particularly heat sensitive components.

Part numbers:  Some component manufacturers show this change by a different part number, a code prefix or suffix but some have not made changes to part numbers

Many older types of component, particularly ICs may not be available as lead-free versions. In some cases, the demand for components is low and RoHS has reduced this to a level where the manufacturer decides to make it obsolete. In either circumstance, this will necessitate circuit redesign to accommodate alternative components. Re-plating lead frames with tin is possible but expensive and so not usually an option.  Software rewrite may also be required for processor ICs.

Early component obsolescence is increasingly an issue for electronics manufacturers. Life-time-buys are an option as a last resort but are usually unacceptable in the longer term. Some circuit designers of equipment intended to be on the market for many years are planning for such eventualities by designing circuits in such a way that when a critical component becomes obsolete, it can easily be replaced by a substitute.

4 Land Pattern Design Standard (IPC 7351 A)

The electronics industry thrives on change and the introduction of new products and processes. In this section some time will be spend examining an area of PCB which is often taken for granted but can be a critical determinant in the success of the final product.

For each package type as described previously, and for those not described, there must be a solder land connection (pad) for each contact. The pattern can either meet all the standard requirements for electronic assembly of fail to meet these requirements..

Data sheets for components or dimensions for land patterns on boards may use other dimensioning concepts; however, the goal is to combine all concepts into a single system.  Where one set of data can be used from PCB design to assembly.

The aim is for industry standard land library across all CAD tool platforms, which will be accepted by the electronics industry to eliminate duplication of effort and automate all of the engineering, design layout, manufacturing and assembly processes.

  4.1 Land Pattern Naming Convention

There are many standards organisations throughout the world and they to are now beginning to standardise. IPC-7351 provides an intelligent land pattern naming convention that not only aids in the standardization of electronic schematic symbols form engineering, but also communicates component information between engineering, design and manufacturing. The aim of this naming convention is to ensure that  all component manufacturers, PCB designers and PCB manufacturers are all following a similar route.

The section of a table below illustrates the naming format

Table 2

IPC-7351A Surface Mount Land Patterns (part)

Component, Category                                          Land Pattern Name

4.2 Land Pattern Syntax Naming Explanations

The syntax which is followed in the land naming is as below.  It is expected that this will cover all eventualities.

The + (plus sign) stands for “in addition to” (no space between the prefix and the body size)

The _ (underscore) is the separator between the Prefix and the Mfr Part Number.

The – (dash) is used to separate the pin qty.

The X (capital letter X) is used instead of the word “by” to separate two numbers such as height X width like “Quad Packages”.

In large connector such as AMP, MOLEX and SAMTEC the “Series Number” is used and the pin qty.   e.g. Molex Example: 90663-60

SUFFIXES For every common SMT land pattern are used to describe environment use (This is the last character in every name)

             • M......................Most Material Condition (Level A)

             • N......................Nominal Material Condition (Level B)

             • L.......................Least Material Condition (Level C)

SUFFIXES for Alternate Components that do not follow the JEDEC, EIA or IEC Standard

            • A......................Alternate Component (used primarily for SOP & QFP when Component Tolerance or Lead Size is different)

            • B......................Second Alternate Component

SUFFIXES for JEDEC and EIA Standard parts that have several alternate packages

            • AA , AB, AC.....JEDEC or EIA Component Identifier (Used primarily on QFN and SON component families)

GENERAL SUFFIXES

            • _VIA ...........Vias (Mounting Holes with 8 vias

             - Example: MTG370X700_VIA

            • _HS ...........HS will be placed between Pin Qty and Environment

             - Example: TO254P1340X300_HS-6N

            • _BEC ........BEC = Base, Emitter and Collector (Pin assignments used for three pin Transistors)

            • _SGD .......SGD = Source, Gate and Drain (Pin assignments used for three pin Transistors)

            • _321 .........321 = Alternate pin assignments used for three pin Transistors

            - Example: SOT95P285X240_321-3N

Therefore, the land pattern name QFP80P+1720 X 2320-80N conveys the following information:

The component family prefix of QFP

The component pin pitch of 0.80 mm

The component lead span nominal X = 17.20 mm for “1720”

The component lead span nominal Y = 23.20 mm for “2320”

The total component pin quantity of 80 pins

The median (nominal) land pattern geometry

4.3 Land Pattern Sizing and Type

The calculation of the land pattern for any particular connection is a mathematically rigorous business.  The tolerance in the manufactures design of the components and the component connections points must be analysed and considered to provide the optimum solution.  The providing of tolerancing information is one area where the standard aims to improve.  All manufacturers do not currently give information in the same manner.

To do this successfully certain parameters must be named in a common format.  Some of these are as illustrated in the diagrams below:

Figure 12: Pitch and Lead Span Measurements

 

Solder Joint Tolerance is for the inside dimension between the component terminal. It is normally represented by the “S” symbol. This is used to calculate the “HEEL” solder joint.

Figure 13: Component Inside Measurement

 

The “G” dimension is used to calculate the minimum and maximum inside spacing of the solder pad. The “Z” dimension is used to calculate the minimum and maximum outside spacing of the solder pad.

Figure 14: Typical Solder Pad Measurements

 

This information is then statistically analysed together with the required solder fillet details’

Where the details are such that, J is the desired dimension of solder fillet or land protrusion;

• J_T   is the solder fillet or land protrusion at toe;
• J_H is the solder fillet or land protrusion at heel;
• J_s is the solder fillet or land protrusion at side;

These dimensions together with the geometry concepts as described below are used to provide optimum sizes for the land patterns for the application required.  The reference that follows should be read for more details as to the actual statistical analysis.  As we progress it will become apparent that the ‘sums’ do not need to be completed each time.

IPC-7351 provides the following three land pattern geometry concepts for each component that the user may select from:

Density Level A: Maximum (Most) Land Protrusion - for high component density applications typical of portable/hand-held products and products exposed to high shock or vibration. The solder pattern is the most robust and can be easily reworked if necessary. Developed to accommodate wave or flow solder of leadless chip devices and leaded gull- wing devices.

Density Level B: Median (Nominal) Land Protrusion — for products with a moderate level of component density and providing a robust solder attachment. The median land patterns furnished for all device families will provide a robust solder attachment condition for reflow solder processes and should provide a condition suitable for wave or reflow soldering of leadless chip and leaded gull-wing type devices.

Density Level C: Minimum (Least) Land Protrusion —for miniature devices where the land pattern has the least amount of solder pattern to achieve the highest component packing density. Selection of the minimum land pattern geometry may not be suitable for all product use categories.

These are as illustrated in the diagrams below for a gull wing device.  The clear difference in the pad sizing can be seen:

Figure 15: Examples of Differing Density Level Requirements

 

4.4 Placement Courtyard

The main purpose of the placement courtyard is to give a guideline for placing land patterns next to each other with enough room to compensate for component tolerances when laying out the PCB.

Courtyard outlines ensure all parts will fit on the board, but they do not compensate for assembly machine heads and manufacturing allowances requirements during manufacture. Each assembler has an individual process. Placement Courtyards are not must not touch or overlap.

The standard courtyard line width is placed on a layer designated by the CAD tool. It is used solely as a visual graphic aid for part placement and never post processed.

The illustration below shows the Component Boundary, the Minimum Courtyard Excess and the Manufacturing Allowance.

Figure16: Placement Courtyard Example

 

The Courtyard Manufacturing zone is critical for the assembly process. It is clearance that must be set for Design Rule Checking. The size of the manufacturing tolerance must come from the assembly processor.  Each has different tolerances; with an average is 0.1mm. The assembly process makes it very difficult to determine placement courtyards for through hole components due to wave soldering constraints.

Therefore, building in placement courtyards for through hole parts is almost impossible due to too many variables. A PCB designer must use common standard rules provided by the assembly processor. The assembly processor should always approve the part placement prior to routing any traces on the board.

4.4 Other features of IPC 7351A

As part of the standardisation process there are other features which will also come into the areas covered by the standard.

• Design Guidance and Assembly Considerations
• design guidance is given for fiducial marks as well as vias under components and within lands. The standard also addresses assembly considerations by including laser cut stencil developments and solder preforms, as well as covering solder processes such as laser and conduction reflow soldering.

• Zero Component rotations
• These are designed to allow CAD land patterns to be built with the same rotation for the purpose of assembly machine automation. The rotations will be defined in terms of the CAD component library with respect to a specific PCB design. This requires that a single land pattern may be used for the same component part from different suppliers and that each supplier may have different orientations on their reels or trays.

• Some examples of this standard
• Chip Capacitors, Resistors and Inductors – Pin 1 on Left
• TO252 & TO263 (DPAK Type) Devices – Upper Left
• Small Outline Gullwing ICs (SOIC, SOP, TSOP, SSOP) – Upper Left
• Ceramic Flat Packs (CFP) – Pin 1 Upper Left
• Small Outline J Lead ICs (SOJ) – Pin 1 Upper Left
• Quad Flat Pack ICs (PQFP, SQFP) – Pin 1 Upper Left

4.5 Land Pattern Software

It can be seen from the above that  this is all very complex. To enable a greater uptake of the standard as software package has been produced.

The Land Pattern Viewer is a key component of IPC- 7351. It is a shareware program that allows users to view component and land pattern dimensional data for standardised component families in tabular form as well as through graphical images that illustrate how a component is attached to the land pattern on the board.

The Land Pattern Viewer provides a specific component and land pattern graphic for each land pattern geometry and is built using the dimensions and tolerance for that part. The Viewer also provides search capabilities among multiple component libraries, aided by the land pattern naming convention. Users can look up components and land patterns by searching on such attributes as pin pitch, pin quantity, part name or lead span, to name a few.

The viewer displays component as well as land pattern dimensional data for a given component. Some of the typical screens are as shown below for a SOIC127P1199x264-24N package.

Figure 17: Sample Screen from IPC – 7351 Viewer

 

The side part of the package gives useful information.

The final use is to provide a full set of data relating to the land pattern as shown below.

Figure 19: Full Set of Data for Component Package

 

The IPC-7351 Land Pattern Viewer relies on library files, know as .p files, for component and land pattern dimensional data. For more information and to download a copy of the program (recommended) and data  on supplemental calculators and library generators  goto http://landpatterns.ipc.org/default.asp  or http://www.pcblibraries.com .  It is worth downloading this for the standards , if you wish to design your own pad based on the techniques shown then you must purchase at extra cost the extra options.

5 Summary

In this unit some of the issues which may seem peripheral to the PCB designers work but it is necessary to be aware of these issues which may come before or after the designers involvement to ensure due care and attention is taken with these points.

All products must be manufactured whether in large or small quantities and the manufacturing method affects the design approach of the PCB.

Packaging is an ever changing issue in the quest for reduced size increased power etc.  A PCB designer will ALWAYS have to update packages of components and deal with new devices. The IPC-7351 standard is a current attempt to address this with a standard which it is hoped will enable efficient first time design for new packaging.

Appendix 1

Summary of Some Common Packaging Options

[1] Tomb-stoning or other undesirable chip movements may result if unequal surface tension forces exist as the molten solder wets the terminations and mounting pads.

[2] A solder bridge is a mechanical bridge formed by solder alloy between two component terminals resulting in an electrical short and circuit malfunction.

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