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Design for EMC & LVD

Design for EMC and LVD

Unit 02: Design for LVD- Switched Mode Power Supply

In this unit we shall design a PCB mounted switched mode power supply to comply with the appropriate standards associated with the LVD Directive. We shall consider the whole of the product's LVD requirements.

The product is assumed to be a rack construction, with a back plane which houses the system PCBs. It is assumed that the product requires the use of a switched mode power supply because of efficiency requirements.

The switched mode power supply used is assumed to be of the fly back type and the input mains voltage is assumed to be in the range 115V to 240V, 50Hz to 60Hz nominal.

 

Key Information

The switch mode power supply is not completely designed in this module- only those aspects of the design that are affected by the LVD Directive are considered.

 

In this unit components are selected and PCB traces are designed to comply with LVD requirements. In subsequent units we shall use the same switched more power supply circuit to illustrate surge protection and harmonic suppression techniques, etc. When this is done we shall modify PCB layout and add components as necessary.

 

Unit Contents

2.1 The Product Overview

We shall call the product X1, for ease of reference. The physical arrangement of product X1 is shown in Fig2.1.

Figure 2.1 Physical Arrangement of Product X1

Figure 2.1 Physical Arrangement of Product X1

Fig 2.1 (a) shows the back plane/PCB arrangement. The switched mode power supply is assumed to be on the first PCB card in the back plane. The back plane has connectors mounted on it and PCBs, which have mating connectors mounted on them, are inserted into the back plane in the correct positions.

Fig 2.1 (b) shows the "LVD components" for the product. We shall assume that we supply the connecting lead with the product correctly terminated with a mains plug and a mains connector that is inserted into the power connector on the product case. Note that the mains cable and internal cabling are included as LVD components. The case, which we shall assume to be metal, is also an LVD component. Clearances between PCBs and PCBs and the metal case must be specified in the design and controlled during manufacture.

We shall assume that the switched mode power supply delivers 5V at a d.c. current of 4Amps- i.e. 20W

 

A switched mode power supply has been chosen because:

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2.2 Switched Mode Power Supply (SMPS) Outline Circuit

Figure 2.2 The Outline Circuit of the Switched Mode Power Supply used in Product X1

Figure 2.2 The Outline Circuit of the Switched Mode Power Supply used in Product X1

The circuit shown in Fig 2.2 is of the fly back type: energy is stored in the core of the isolating transformer TX1, while the transistor TR1 is conducting. When TR1 is turned off the stored energy, which is actually stored in the magnetic core of TX1, is transferred to the secondary winding. This produces a large, positive going, voltage spike at the drain of TR1. If the diode D1 and Zener ZD1 were not included in the circuit the amplitude of the spike would be controlled by the circuit stray capacitance Cs, between source and drain. Under these circumstances there is a danger that the breakdown voltage of TR1 would be exceeded. Diode D1 and zener diode ZD1 clamp the voltage to a safe value. The fly back action transfers energy to the secondary winding W3 which is rectified and smoothed to provide the output voltage of the power supply. Winding W3 on TX1 produces a feedback voltage which is compared with an internal power supply reference to control the power supply output voltage.

The components in Fig 2.2 have the following function(s):

Fuse F1

Protects against over currents- especially when critical components fail.

Bridge Rectifier BR1

Converts the a.c. mains voltage to unidirectional voltage.

Capacitor C1

Smooths the bride rectifier output voltage to provide an unregulated direct voltage - this is usually a polarised device.

Transistor TR1

Used in switching mode to store energy in the magnetic core of TX1, when it is conducting and to convert this energy to useful output, via winding W3, when it is switched off. Control of the voltage output is usually obtained by adjusting the on to off time of TR1, that is by adjusting the duty cycle of TR1. Note that the switching frequency of TR1 is high and of the order of 100KHz. This ensures that the physical size of TX1 is small.

Transformer TX1

The transformer provides electrical (galvanic) isolation- it isolates the high voltage components and PCB traces from the low voltage zones of the PCB and the product as a whole.

 

The primary winding is used to define the stored energy and convert this to useful output when fly back occurs.

The output of the secondary winding W3, is rectified and smoothed to produce the power supply output voltage.

The output of the feedback winding W2, is rectified and smoothed to produce a feedback back voltage that allows the SMPS to control the regulated power supply output voltage.

Note: the sense of the windings is important, the "dot convention" used in Fig 2.2 specifies the winding sense, that is the polarities of the secondary and feedback windings relative the voltage applied the primary winding.

The transformer core material must have low losses at high frequencies and for this reason a ferrite material is normally used.

The high operating frequency of the transformer ensures it is physically small.

Insulation requirements for the transformer are critical- it provides isolation for the whole of the product.

Diode D1 and Zener Diode Z1

The components limit the fly back voltage to a safe value, ensuring that transistor TR1 is not over stressed, thus avoiding drain to source breakdown of the switching FET. The limiting action is often referred to as "snubbing" and a number of alternative snubbing networks are available.

 

Diode D1 must have a high breakdown voltage and a fast turn on/off time. The breakdown voltage of the zener diode is chosen to control the fly back voltage.

Diode D3 and Capacitor C3

The devices are used to rectify and smooth the SMPS output voltage. In practice , extra smoothing, that is filtering, is required but this is not shown in Fig 2.2.

Diode D2 and Capacitor C2

These components are used to rectify and smooth the feedback voltage. Note the current loading on the smoothing components is small. Additional filtering may take place in the SMPS IC.

SMPS Internal Control Circuitry

The switched mode power supply internal control circuitry is complex and typically provides the following functions:

High Voltage Zone Circuit Reference

This high voltage circuit reference must not be connected to the protective earth. Sufficient clearance and creepage distances must be placed between the the high voltage zone and the rest of the product.

Protective Earth

The metal case case must be securely bonded to the protective earth lead of the mains supply.

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2.3 Simplified Circuit Operation

In this section we shall develop some simplified equations that allow us to choose values for LVD components.

 

\[ \begin{gathered} {\text{The output power }}P_{OUT} = V_{OUT} I_L ...................................................................2.1 \hfill \\ \hfill \\ {\text{Assume the rectifier output voltage is }}V_{DC} \hfill \\ \hfill \\ {\text{When the transistor }}T_{R1} {\text{ is switched on we have:}} \hfill \\ V_{DC} = L_P \frac{{di_P }} {{dt}},{\text{where }}i_P {\text{ = the transformer primary current}} \hfill \\ \hfill \\ L_P {\text{ = the self inductance of the transformer primary winding}} \hfill \\ \therefore i_P = \frac{{V_{DC} }} {{L_P }}t \hfill \\ \hfill \\ {\text{and }}I_P = \frac{{V_{DC} }} {{L_P }}T_{ON} \hfill \\ {\text{where }}I_P {\text{ = the peak drain current at the end of the transistor on time }}T_{ON} \hfill \\ \hfill \\ {\text{We must ensure that the transistor peak current is less than the maximum allowed}} \hfill \\ {\text{drain current: }}I_P < I_{DSMAX} .......................................................................2.2 \hfill \\ \hfill \\ {\text{The energy stored in the core at the end of the transistor on time is:}} \hfill \\ E_P = \frac{1} {2}L_P I_P^2 \hfill \\ \end{gathered} \]

Voltage and current waveforms for the fly back state are shown in Fig 2.3. When transistor TR1 is on the voltage across it is small- we have assumed it zero in the first instance. Current flows in the primary winding W1 and it has a triangular wave shape. While current is flowing in W1 there is a back emf induced in it by the changing flux in the transformer core.

The changing flux also induces a voltage in the secondary and feedback windings, but the sense of the windings ensures this is negative, which reverse biases the diodes D2 and D3. Consequently the current in both these windings is zero, while TR3 is on.

Figure 2.3 Primary and Secondary Voltage and Current Waveforms for the Fly back SMPS: Discontinuous Mode

Figure 2.3 Primary and Secondary Voltage and Current Waveforms for the Fly back SMPS: Discontinuous Mode

At the end of TON, transistor TR1 is turned off quickly, we have assumed turn off time is zero. The applied voltage to W1 is removed but the magnetic flux is stored in the core of the transformer. The transformer core now becomes a source of energy. As the flux in the core starts to decay a voltage is induced in winding W1 proportional to the rate of change of flux, which is now negative- the flux is decaying. The voltage at the drain of TR1 rises rapidly and while this is happening the current flowing in the primary winding flows in the stray capacitance at the drain node. If the zener clamp voltage and the output and feedback windings were not present this energy in the core would be transferred to this stray capacitance.

 

\[ \begin{gathered} {\text{If }}C_S {\text{ = the stray capacitance across transistor TR3, and we assume all the energy}} \hfill \\ {\text{stored in the inductor is transferred to it, we have:}} \hfill \\ \hfill \\ \frac{1} {2}L_P I_P^2 = \frac{1} {2}C_S V_{CS}^2 \hfill \\ \hfill \\ \therefore V_{CS} = \sqrt {\frac{{L_P }} {{C_S }}} I_P \hfill \\ \hfill \\ {\text{If we assume typical values as }}L_P = 500\mu H,{\text{ }}C_S = 10pF{\text{ and }}I_P = 1{\text{ }}A, \hfill \\ \hfill \\ V_{CS} = 7KV,{\text{ which would of course destroy the switching transistor}}{\text{.}} \hfill \\ \end{gathered} \]

This is why we need the snubber circuit, D1, Z1, to clamp the drain voltage to a safe value.

 

However, both D1 and Z1 have a finite response time, so the voltage across them in the forward direction overshoots the clamping voltage. The inductor now becomes a source of energy and the back emf, which is related to the changing flux in the transformer core causes the drain voltage to rise rapidly. Note the polarity of the induced emf is opposite to that of the applied voltage. The voltage across W1 continues to rise as energy in the core is transferred to any stray capacitance between drain and the source of TR1. The voltage rises above the zener clamping voltage and continues to rise until diode D1 becomes forward biased.

The overshoot shown in Fig 2.3 is a consequence of the diode D1 and zener diode Z1 response times. Both these diodes should be chosen to have very fast response times.

The sign of the voltages induced in windings W2 and W3 also changes sign when TR1 switches off. However, diodes D2 and D3 have a finite response time so they do not have time to enter the conduction mode, i.e. they do not have time to recover, on the switching edge of the waveform, even though they are forward biased.

In the following discussion we shall consider only the secondary winding W3, waveforms in winding W2 are similar. When diode D3 enters the conduction mode the voltage across W3 is held virtually constant by capacitor C3, the reservoir capacitor of the supply output circuit. If we neglect the volt drop across diode D3, this is VOUT. This voltage, is reflected back into the primary winding by the turns ratio of the transformer as VOUTR, see Fig2.3.

Current flows in the primary winding while TR3 is on and in the secondary winding when TR3 is off. Hence the transformer is not acting like a conventional transformer and is really behaving as a coupled inductor. If the current in the secondary winding W3 falls to zero before the end of the transistor off time, TOFF, all the energy stored in the transformer core has been transferred to the secondary winding circuit or dissipated in the transformer, the transistor and diodes. This fly back mode is know as the discontinuous mode, if the current in the secondary had not reached zero at the end of TOFF, the circuit would have been operating in the continuous mode.

We shall assume the circuit works in the discontinuous mode.

When operating in discontinuous mode ringing occurs when the current in the secondary falls to zero. This is caused by the the stray capacitance resonating with transformer inductances.

We can use Fig 2.3 to develop some simple equations that define the voltage levels for the switching transistor, TR1.

\[ \begin{gathered} {\text{If the breakdown voltage of the switching FET is }}BV_{DSS} \hfill \\ \hfill \\ BV_{DSS} = Vac_{\max } + V_{CLAMP} + V_{OS} + V_{SM} ............................................2.3 \hfill \\ \hfill \\ {\text{Where }}V_{SM} = {\text{safety margin}} \hfill \\ {\text{Also, }}V_{OUTR} = \frac{{N_P }} {{N_S }}\left( {V_{OUT} + V_{FD3} } \right)...................................................2.4 \hfill \\ \hfill \\ {\text{Where }}V_{FD3} = {\text{ the voltdrop across diode D3 when it is forward biased}} \hfill \\ \end{gathered} \]

 

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2.4 The Isolating Transformer

We shall assume that the isolating transformer core is of the E type, as shown in Fig 3.4, and that the core material is ferrite, to reduce core losses at high frequencies.

Figure 2.4 Standard Transformer E Core

 

Figure 2.4 Standard Transformer E Core

Dimension shown are specified by the core manufacturer. A complete transformer core is, made up of 2 E cores is shown in Fig 2.6 (a). Note that the centre limb sections are separated by an air gap. This ensure the energy storage within the core is high.

$\begin{gathered} {\text{Assume the following:}} \hfill \\ B_{\max } {\text{ = the maximum flux density in the core}} \hfill \\ Ae{\text{ = of cross sectional area on the centre limb}} \hfill \\ {\text{Lg = gap length}} \hfill \\ {\text{The energy density in the gap is given by: E}}_{\text{D}} {\text{ = }}\frac{{{\text{B}}_{{\text{max}}}^{\text{2}} }} {{2\mu _0 }}{\text{ Joules/m}}^{\text{3}} \hfill \\ \hfill \\ {\text{The energy stored in the gap }}Eg{\text{ }} = {\text{ }}E_D \times {\text{Volume of gap}} \hfill \\ \hfill \\ {\text{Eg = }}\frac{{{\text{B}}_{{\text{max}}}^{\text{2}} AeLg}} {{2\mu _0 }} \hfill \\ \hfill \\ {\text{Alternatively, }}L_P = \frac{{N_P^2 }} {s},{\text{ where s = the reluctance of the magnetic circuit}} \hfill \\ \hfill \\ s = \frac{{Lg}} {{\mu _0 Ae}} \hfill \\ \hfill \\ {\text{Hence }}Lg = \frac{{N_P^2 \mu _0 Ae}} {{L_P }} \times 1000{\text{ mm }}..........................................................{\text{2}}{\text{.5}} \hfill \\ \end{gathered} $

We need to store energy in the core when TR3 is on, which will be transferred to the secondary winding output circuit when TR3 is off.

Figure 2.5 Typical Core and Bobbin Arrangement for a SMPS Isolating Transformer

 

Figure 2.5 Typical Core and Bobbin Arrangement for a SMPS Isolating Transformer

Fig 2.5 (b) shows the core with an insulating winding bobbin in place and winding connection pins. Bobbin size must be specified in the transformer design and be consistent with core dimensions.

Fig 2.6 (a) shows the winding and insulating outline information: the core has been omitted for clarity.

Figure 2.6 Typical Winding Arrangement for a SMPS Isolating Transformer

Figure 2.6 Typical Winding Arrangement for a SMPS Isolating Transformer

Fig 2.6 (b) shows a cross section through the bobbin and provides more detailed information about winding, insulation and winding sense. Care should be taken in specifying winding starts and finishes and the winding sense.

A creepage margin has been shown at both ends of the secondary winding. This has to be set to comply with regulatory requirements, as we shall see shortly.

We need to know the RMS primary and secondary currents in order to determine the diameter of the wire used for the transformer windings. We shall start by evaluating the primary average current, remembering that current only flows in the primary winding when TR1 is on.

 

\[ \begin{gathered} {\text{We have seen that }}i_P = \frac{{V_{DC} }} {{L_P }}t \hfill \\ {\text{The average primary current is given by:}} \hfill \\ I_{P(AVE)} = \frac{1} {{T_{SW} }}\int\limits_0^{T_{ON} } {i_P } dt \hfill \\ {\text{Where }}T_{SW} {\text{ is the period of the transistor switching waveform}} \hfill \\ \therefore I_{P(AVE)} = \frac{1} {{T_{SW} }}\int\limits_0^{T_{ON} } {\frac{{V_{DC} }} {{L_P }}t} dt = \frac{{V_{DC} }} {{T_{SW} L_P }}\left[ {\frac{{t^2 }} {2}} \right]_0^{T_{ON} } \hfill \\ \hfill \\ I_{P(AVE)} = \frac{{V_{DC} T_{ON}^2 }} {{2L_P T_{SW} }}{\text{ and }}\frac{{{\text{T}}_{{\text{ON}}} }} {{{\text{T}}_{{\text{SW}}} }} = D,{\text{ the duty cycle}} \hfill \\ \hfill \\ \therefore I_{P(AVE)} = \frac{{V_{DC} T_{ON} T_{ON} }} {{2L_P T_{SW} }} = \frac{{V_{DC} T_{ON} D}} {{2L_P }} \hfill \\ \hfill \\ {\text{and }}I_{P(AVE)} = \frac{{I_P D}} {2} \hfill \\ \end{gathered} \]

 

We shall now develop an equation for the RMS current flowing in the primary winding.

 

$\begin{gathered} {\text{To calculate the RMS value of the primary current, we first take the mean of the}} \hfill \\ {\text{square of the instantaneous current:}} \hfill \\ \hfill \\ I_{P(RMS)}^2 = \frac{1} {{T_{SW} }}\int\limits_0^{T_{ON} } {i_P^2 } dt = \frac{{V_{DC}^2 }} {{L_P^2 }}\int\limits_0^{T_{ON} } {t^2 dt} = \frac{{V_{DC}^2 }} {{T_{SW} L_P^2 }}\left[ {\frac{{t^3 }} {3}} \right]_0^{T_{ON} } = \frac{{V_{DC}^2 }} {{T_{SW} L_P^2 }}\frac{{T_{ON}^3 }} {3} \hfill \\ \hfill \\ I_{P(RMS)}^2 = \frac{{V_{DC}^2 T_{ON}^2 }} {{3L_P^2 }}\frac{{T_{ON} }} {{T_{SW} }} = \frac{{V_{DC}^2 T_{ON}^2 }} {{3L_P^2 }}D \hfill \\ \hfill \\ I_{P(RMS)} = \frac{{V_{DC} T_{ON} }} {{L_P }}\sqrt {\frac{D} {3}} \hfill \\ \hfill \\ I_{P(RMS)} = I_P \sqrt {\frac{D} {3}} ......................................................................................2.6 \hfill \\ \end{gathered} $

$\begin{gathered} {\text{To calculate the secondary average and rms currents we note that:}} \hfill \\ I_S N_S = I_P N_P {\text{ }}\therefore I_S = I_P \frac{{N_P }} {{N_S }} \hfill \\ {\text{Carrying out a similar analysis to that used for evaluating the primary average and RMS}} \hfill \\ {\text{currents yields:}} \hfill \\ I_{S(AVE)} = \frac{{I_S }} {2}\frac{{T_{OFF} }} {{T_{SW} }} = \frac{{I_S }} {2}\frac{{\left( {T_{SW} - T_{ON} } \right)}} {{T_{SW} }} \hfill \\ \hfill \\ I_{S(AVE)} = \frac{{I_S \left( {1 - D} \right)}} {2}...........................................................................2.7 \hfill \\ I_{S(RMS)} = I_S \sqrt {\frac{{1 - D}} {3}} ............................................................................2.8 \hfill \\ \end{gathered} $

 

We shall now determine the transformer voltage stress, which is illustrated in Fig 2.7.

Figure 2.7 Illustrating Transformer Voltage Stress

 

Figure 2.7 Illustrating Transformer Voltage Stress

 

$\begin{gathered} {\text{The maximum voltage applied to the primary winding is, from Fig 2}}{\text{.3:}} \hfill \\ \hfill \\ V_{PMAX} = Vac_{\max } + V_{CLAMP} + V_{OS} \hfill \\ \hfill \\ {\text{Assuming the voltage is distributed evenly across th primary winding, the volts/turn is:}} \hfill \\ \hfill \\ V_{TP} {\text{ }} = \frac{{V_{PMAX} }} {{N_P }}........................................................................................2.9 \hfill \\ {\text{where }}V_{TP} {\text{ = the volts/turn for the primary winding}} \hfill \\ \hfill \\ {\text{The voltage stress between the primary start and finish, when there are 2 primary layers}} \hfill \\ {\text{is }}V_{PMAX} \hfill \\ \hfill \\ {\text{If there are more than 2 layers, the stress between 2 adjacent layers is }}2 \times \frac{{V_{PMAX} }} {{N_P }} \times N_{TL} {\text{ }} \hfill \\ V_{PS} = 2 \times \frac{{V_{PMAX} }} {{N_P }} \times N_{TL} {\text{ }}........................................................................{\text{2}}{\text{.10}} \hfill \\ {\text{Where }}N_{TL} {\text{ = the number of primary turns/layer}} \hfill \\ \hfill \\ {\text{The voltage stress between primary and secondary winding is:}} \hfill \\ \hfill \\ V_{PS} = V_{PMAX} ..........................................................................................2.11 \hfill \\ {\text{Where }}V_{PS} {\text{ = the voltage stress between the primary and secondary windings}} \hfill \\ \end{gathered} $

 

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2.5 The Input Rectifier Circuit

The input rectifier circuit is made up of the full wave bridge rectifier BR1 and the storage capacitor C1, shown in Fig 2.2.

Voltage and capacitor current waveforms are shown in Fig 2.8. The ripple voltage is Vr volts peak to peak. Note that when the rectifier BR1 starts to conduct the rate of change of voltage across C1 is dVac/dt volts/second.

Figure 2.8 Input Rectifier Voltage and Current Waveforms

 

Figure 2.8 Input Rectifier Voltage and Current Waveforms

\[ \begin{gathered} {\text{The input mains voltage is }}v = \mathop V\limits^ \wedge Sin\omega t \hfill \\ \hfill \\ {\text{ The rate of change of voltage across }}C1{\text{, neglecting the diode volt drops, is }}\frac{{dv}} {{dt}} = \omega \mathop V\limits^ \wedge Cos\omega t \hfill \\ \hfill \\ {\text{When }}t = T_1 ,{\text{ }}\frac{{dv}} {{dt}} = \omega \mathop V\limits^ \wedge Cos\omega T_1 {\text{ and the diodes start to conduct}} \hfill \\ \hfill \\ {\text{Note that }}ic = C1\frac{{dv}} {{dt}},{\text{ where }}ic{\text{ = the instantaneous current in }}C1 \hfill \\ \hfill \\ {\text{The time that the bridge starts to conuct is given by:}} \hfill \\ T_1 = \frac{1} {{2\pi f}}Sin^{ - 1} \left( {\frac{{\mathop {\text{V}}\limits^ \wedge - Vr}} {{\mathop {\text{V}}\limits^ \wedge }}} \right)................................................................................2.12 \hfill \\ {\text{and }}\mathop I\limits^ \wedge _C = C_1 \omega \mathop V\limits^ \wedge Cos\omega T_1 ..................................................................................2.13 \hfill \\ {\text{Where }}\mathop I\limits^ \wedge _C {\text{ is the peak current flowing in capacitor }}C1. \hfill \\ \hfill \\ {\text{The time between rectifier pulses is }}T_{BR1\_0FF} = \frac{T} {4} + T_1 ......................................2.14 \hfill \\ \hfill \\ {\text{The number of FET conduction pulses in }}T_{BR1\_0FF} = M_P = \frac{{T_{BR1\_0FF} }} {{T_{SW} }}...............2.15 \hfill \\ {\text{The charge taken form the capacitor C1 during a single FET on pulse is:}} \hfill \\ \hfill \\ dq = \int\limits_0^{T_{ON} } {i_P } dt \hfill \\ \hfill \\ dq = \frac{{V_{DC} }} {{2_{LP} }}\left( {T_{SW} D} \right)^2 .........................................................................................2.16 \hfill \\ \hfill \\ {\text{Total charge taken from C1 during }}T_{BR1\_0FF} = Delat\_Q = M_P dq...................2.17 \hfill \\ \hfill \\ {\text{C1 = }}\frac{{Delat\_Q}} {{Vr}} = \frac{{M_P dq}} {{Vr}}..................................................................................2.18 \hfill \\ \end{gathered} \]

The voltage across the input diodes, when they are reverse biased is:

 

 

\[ \begin{gathered} V_{RB} = V_{DC} + Vac\max ,{\text{ wher VRB is the reverse bias applied to the non - conducting}} \hfill \\ {\text{diodes in the bridge rectifier}} \hfill \\ \hfill \\ {\text{and }}V_{DC} \max \approx Vac\max ,{\text{ hence }} \hfill \\ \hfill \\ V_{RB} = 2Vac(\max ),{\text{ which is applied to 2 diodes in series}}............................{\text{2}}{\text{.19}} \hfill \\ \hfill \\ \end{gathered} \]

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2.6 Power Relationships

In this section we shall develop relationships for the output and input power and also for power losses in various components.

Power Input and Output Relationships

 

$\begin{gathered} {\text{Let the output load current of the supply be I}}_{\text{L}} {\text{, and the output voltage V}}_{{\text{OUT}}} \hfill \\ \hfill \\ {\text{The output power of the supply, P}}_{{\text{OUT}}} {\text{ = V}}_{{\text{OUT}}} {\text{I}}_{\text{L}} .............................................2.1 \hfill \\ \hfill \\ {\text{Both V}}_{{\text{OUT}}} {\text{ and I}}_{\text{L}} {\text{ are d}}{\text{.c}}{\text{. values}}{\text{. V}}_{{\text{OUT }}} {\text{is held virtually constant by the SMPS chip,}} \hfill \\ {\text{the output rectifier circuit and the output filter}}{\text{.}} \hfill \\ \hfill \\ {\text{I}}_{\text{L}} {\text{ varies as the load varies and is determined by the average current flowing in the}} \hfill \\ {\text{secondary winding}}{\text{.}} \hfill \\ \hfill \\ {\text{I}}_{\text{L}} {\text{ = I}}_{{\text{S(AVE)}}} {\text{ = }}\frac{{{\text{I}}_{\text{S}} {\text{(1 - D)}}}} {{\text{2}}} \hfill \\ \hfill \\ {\text{P}}_{{\text{OUT}}} {\text{ = }}\frac{{{\text{V}}_{{\text{OUT}}} {\text{I}}_{\text{S}} {\text{(1 - D)}}}} {{\text{2}}} \hfill \\ \hfill \\ {\text{The input power to the supply P}}_{{\text{IN}}} {\text{ = V}}_{{\text{AC(RAMS)}}} {\text{I}}_{{\text{AC(RMS)}}} \hfill \\ \hfill \\ {\text{If the efficiency of the supply = }}\eta {\text{,}} \hfill \\ \hfill \\ \eta = \frac{{POUT}} {{PIN}} = \frac{{V_{OUT} I_L }} {{{\text{V}}_{{\text{AC(RAMS)}}} {\text{I}}_{{\text{AC(RMS)}}} }} \hfill \\ \end{gathered} $

Transformer Losses

Transformer losses are of two types:

 

Note that the core material of high frequency transformers is usually ferrite, which reduces eddy current losses in the core. We shall start by evaluating the winding copper losses.

 

Copper Losses

\[ \begin{gathered} {\text{Let the primary winding resistance be }}R_P \hfill \\ \hfill \\ {\text{The power dissipated in this winding is:}} \hfill \\ \hfill \\ P_{RP} = I_{P(RMS)}^2 R_P \hfill \\ \hfill \\ Rp = \frac{{\rho l_{PW} }} {{a_{PW} }} = \frac{{\rho NpL_{MPT} }} {{a_{PW} }} \hfill \\ \hfill \\ {\text{A useful design parameter is the allowed current density in the wire, which is typically:}} \hfill \\ \hfill \\ Jd = 5A/mm^2 \hfill \\ \hfill \\ {\text{This allows the diameter of the copper windings to be estimated:}} \hfill \\ \hfill \\ J_d = \mathop I\limits^ \wedge _{(RMS)} /a_W ,{\text{ where }}a_W = {\text{ the cross - sectional area of the wire}} \hfill \\ \hfill \\ a_W = \pi \frac{{d^2 }} {4},{\text{ hence }}d = \sqrt {\frac{{4a_W }} {\pi }} \hfill \\ \therefore d = \sqrt {\frac{{4\mathop I\limits^ \wedge _{(RMS)} }} {{\pi Jd}}} \hfill \\ \hfill \\ {\text{The diameter of the primary winding is: }}d_P = \sqrt {\frac{{4I_{P(RMS)} }} {{\pi Jd}}} ...........................2.20 \hfill \\ \hfill \\ {\text{The diameter of the secondary winding is: }}d_S = \sqrt {\frac{{4I_{S(RMS)} }} {{\pi Jd}}} .......................2.21 \hfill \\ \hfill \\ {\text{At high frequencies current is forced to flow close to the surface of the conductor,}} \hfill \\ {\text{due to the skin effect}}{\text{. The skin depth for copper is given by:}} \hfill \\ \hfill \\ \delta = \sqrt {\frac{1} {{\pi \sigma \mu _0 f}}} \hfill \\ \hfill \\ {\text{When the switching frequency waveform is a square wave, we may write:}} \hfill \\ \hfill \\ \delta _{SW} = \sqrt {\frac{1} {{\pi \sigma \mu _0 f_{SW} }}} {\text{ for the fundamental of the switching waveform}} \hfill \\ \hfill \\ {\text{Note that }}\delta = \frac{{0.067}} {{\sqrt f }}..............................................................{\text{Eq 6}}{\text{.16 AMI4822}} \hfill \\ \end{gathered} \]

Core Losses

Core losses are of two types, hysterisis losses and eddy current losses. We shall start by considering hysterisis losses.

Hysterisis Losses

Magnetic materials may be considered as being made up of numerous small magnetic domains, each with its own north and south pole. Normally the domains are orientated at random and the effects of the small magnets cancel: the material exhibits no magnetic behaviour. When a magnetising force, H, is applied to the core the domains tend align with it and their magnetic fields tend to add. If the magentising force is increased further a point is reached where all the domains are aligned with the magnetising force and the material is said to be saturated. Increasing the magentising force further produces only a small increase in flux.

When the applied voltage to the primary winding is positive the magnetic flux increases and follows path defa. When the applied voltage is negative the flux follows path abcd, because energy is expended in the core rotating the "magnetic domains". The effect is called hysterisis- there are two values of flux for each value of magnetising force, depending on the direction of the magnetising force.

The loop formed by the hysterisis effect is called the B-H loop for the core and the area of the B-H loop represents an energy loss. The area formed by aXba represent stored magnetic energy in the core that will be dissipated during switching.

Figure 2.9 Hysterisis Loss in a Normal Transformer Core

 

Figure 2.9 Hysterisis Loss in a Normal Transformer Core

$\begin{gathered} {\text{The energy supplied to the transformer primary winding is:}} \hfill \\ En = \int {vidt} {\text{ }} \hfill \\ v = {\text{ primary winding voltage}} \hfill \\ i = {\text{ primary winding current}} \hfill \\ \hfill \\ {\text{Also, }}v = N_P \frac{{d\phi }} {{dt}}{\text{ and }}\phi = Ba{\text{, where }}a{\text{ = the core cross sectional area}} \hfill \\ \hfill \\ {\text{Hence }}v = N_P a\frac{{dB}} {{dt}} \hfill \\ {\text{The magnetisng force }}H = \frac{{N_P i}} {l},{\text{ where }}l = {\text{ the length of the core magnetic circuit}} \hfill \\ \hfill \\ \therefore En{\text{ }} = {\text{ }}\int {N_P a\frac{{dB}} {{dt}}} \frac{{Hl}} {{N_P }}dt = {\text{ }}al\int {HdB} ,{\text{ note that al = the volume of the core}} \hfill \\ \hfill \\ {\text{The enegy density is }}\frac{{En}} {{al}} = \int {HdB} {\text{ , Joules/m}}^{\text{3}} \hfill \\ \end{gathered} $

The transformer in a flyback SMPS does not behave like a conventional transformer, current flows in the primary and secondary windings at different times and only a positive voltage is applied to the primary winding. This is shown in Fig 2.10.

Figure 2.10 Hysterisis Loss in a Discontinuous SMPS Transformer

Figure 2.10 Hysterisis Loss in a Discontinuous SMPS Transformer

The transformer operates in a uni-polar mode, both B and H are always positive. Flux increases in the core when transistor TR1 in on and decreases when TR1 is off. The primary and secondary current both fall to zero and the flux changes during both intervals are equal. The B-H loop is a minor loop as shown in Fig 2.10. The energy dissipated in the core depends upon the area of the loop and the switching frequency of TR1. Core manufacturers normally supply graphical and/or tabular information giving total core loss as a function of frequency and flux change. The total core loss includes both hysterisis and eddy current losses. We shall now consider eddy current losses.

Eddy Current Losses

The changing magnetic flux present in the core material induces a voltage in the core itself. This voltage links, that is, embraces the changing flux. The voltage acts around loops within the core and causes electrical currents to circulate within it. These currents are called eddy currents and they produce an energy loss within the core. The value of the currents depends on the core material, the path taken by the circulating currents, and the magnitude of the currents. This is illustrated in Fig 2.11

 

Fig 2.11 (a) shows the flux path in the core and the eddy current path surrounding it. Note that voltage acting on the loop is equal to the rate of change of flux in the area it embraces.

Figure 2.11 Eddy Currents in a Transformer Core

Figure 2.11 Eddy Currents in a Transformer Core

The situation in the core is shown in more detail in Fig2.12. We have considered the voltage acting around a rectangular loop within the core. The voltage acting around the loop produces a current within it. The voltage acting around the loop is equal to the rate of change of magnetic flux it links, or embraces. The current flows in a rectangular "box" of length L. We have set up a co-ordinate system centred on the center of the core.

Figure 2.12 Expanded View of a Voltage and Current Loops in the Core

 

Figure 2.12 Expanded View of a Voltage and Current Loops in the Core

The details of the core are shown in relationship to the co-ordinate system in Fig 2.13.

Figure 2.13 Detail of an Eddy Current Loop in the Core

 

Figure 2.13 Detail of an Eddy Current Loop in the Core

\[ \begin{gathered} {\text{The power dissipated in the loop is:}} \hfill \\ P_{loop} = v_{LOOP} i_{LOOP} \hfill \\ {\text{The voltage induced in the loop is }}v_{LOOP} {\text{ }} = {\text{ }}\frac{{d\phi }} {{dt}} \hfill \\ {\text{If the }}H/W = k{\text{, and }}y/x = k{\text{, the aspect ratio of the core cross - sectional area , then }}dy = kdx \hfill \\ \hfill \\ {\text{The flux that this loop encloses }}\phi {\text{ }} = B2x2y \hfill \\ \therefore \phi {\text{ }} = B2x2kx = 4kBx^2 \hfill \\ v_{LOOP} {\text{ }} = {\text{ }}4kx^2 \frac{{dB}} {{dt}} \hfill \\ \hfill \\ {\mathbf{We shall assume the flux denisty is distributed evenly across the core}} \hfill \\ \hfill \\ {\text{The loop resistance is made up of 4 resistors in series:}} \hfill \\ r_{LOOP} = \frac{{\rho 2y}} {{Ldx}} + \frac{{\rho 2y}} {{Ldx}} + \frac{{\rho 2x}} {{Ldy}} + \frac{{\rho 2x}} {{Ldy}} \hfill \\ \hfill \\ r_{LOOP} = \frac{{4\rho x}} {{Ldx}}\left( {\frac{{1 + k^2 }} {k}} \right) \hfill \\ \hfill \\ g_{LOOP} = \frac{{kLdx}} {{4\rho x\left( {1 + k^2 } \right)}} \hfill \\ \hfill \\ i_{LOOP} = {\text{ }}vi_{LOOP} g_{LOOP} = 4kx^2 \frac{{dB}} {{dt}}\frac{{kLdx}} {{4\rho x\left( {1 + k^2 } \right)}} = \frac{{k^2 Lxdx}} {{\rho \left( {1 + k^2 } \right)}}\frac{{dB}} {{dt}} \hfill \\ \hfill \\ P_{loop} = v_{LOOP} i_{LOOP} {\text{ = }}4kx^2 \frac{{dB}} {{dt}}\frac{{k^2 Lxdx}} {{\rho \left( {1 + k^2 } \right)}}\frac{{dB}} {{dt}} \hfill \\ \hfill \\ P_{loop} = \frac{{4k^3 L}} {{\rho \left( {1 + k^2 } \right)}}\left( {\frac{{dB}} {{dt}}} \right)^2 x^3 dx \hfill \\ \hfill \\ P_{TOTAL} = \frac{{4k^3 L}} {{\rho \left( {1 + k^2 } \right)}}\left( {\frac{{dB}} {{dt}}} \right)^2 \int\limits_0^{w/2} {x^3 } dx = \frac{{4k^3 L}} {{\rho \left( {1 + k^2 } \right)}}\left( {\frac{{dB}} {{dt}}} \right)^2 \left[ {\frac{{x^4 }} {4}} \right]_0^{w/2} \hfill \\ \hfill \\ \therefore P_{TOTAL} = \frac{{k^3 L}} {{16\left( {1 + k^2 } \right)\rho }}\left( {\frac{{dB}} {{dt}}} \right)^2 W^4 \hfill \\ k = \frac{H} {W} \hfill \\ \hfill \\ Power/unit{\text{ volume = }}\frac{{k^2 }} {{16\left( {1 + k^2 } \right)\rho }}\left( {\frac{{dB}} {{dt}}} \right)^2 W^2 \hfill \\ \end{gathered} \]

The eddy current power loss density depends on the the square of the rate of change of flux density and the square of the dimension W and is inversely proportional to the core material resistivity. SMPS operate at high frequency and eddy current loss is made low by using materials with a high resistivity and acceptable magnetic properties.

Total Core Loss

Core loss is difficult to predict analytically, especially in the first pass at a transformer design. Core manufacturers usually produce a set of curves of total core loss as a function of frequency and flux density swing. Note that both hysterisis and eddy current loss depend on these two factors. A typical representation of total core loss is shown in Fig 2.14.

Figure 2.14 Graphical Representation of Total Core Loss

 

Figure 2.14 Graphical Representation of Total Core Loss

 

\[ \begin{gathered} {\text{Normally, manufacturers define flux density as the peak to peak swing for a }} \hfill \\ {\text{sinusoidal excitation}}{\text{. This depends on the the integral }}\int {\frac{{E_P }} {{N_P }}dt} {\text{ }} \hfill \\ \hfill \\ {\text{Note that for a SMPS, }}E_P = N_P \frac{{d\varphi }} {{dt}} = N_P A\frac{{dB}} {{dt}} \hfill \\ \hfill \\ {\text{A = core area}} \hfill \\ \therefore \Delta B = \int\limits_0^{T_{ON} } {\frac{{Ep}} {{N_P A}}dt} {\text{ }} = {\text{ }}\frac{{Ep}} {{N_P A}}T_{ON} = \frac{{EpD}} {{N_P Af_{SW} }} \hfill \\ \hfill \\ {\text{For a SMPS transformer, which operates in unipolar mode, the flux denisty change used to estimate}} \hfill \\ {\text{core loss shold be halved when using the loss curves}}{\text{.}} \hfill \\ {\text{That is }}\frac{{\Delta B}} {2}{\text{ is used to determine total core loss}} \hfill \\ \end{gathered} \]

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2.7 Product Requirements

In this section we shall list the product outline requirements pertinent to the LVD directive.

Power supply output

Output voltage 5V d.c.

Output current 4A d.c maximum

Input Voltage

Mains input -European markets 240V RMS +/- 10% 50Hz +/- 1%

 

Mains input- American Markets 115V RMS +/- 10% 60Hz +/- 1%

 

Ambient temperature range- 5 degC to 40 degC

 

Relative humidity- 80% for temperatures up to 31 degC, decreasing linearly to 50% at 40 degC

2.8 Clearance, Creepage and Insulation Strength

We have assumed the product environment subjects it to pollution degree 2, which allows us to determine clearance and creepage distances:

 

Pollution degree 2, Material Group 1, Table 4, page 44, EN61010-1:2001

For a.c. mains voltages- 240V rms use row for > 150 < 300 volts rms.

Clearance distance 1.5 mm

Creepage Distance PWB 1.5 mm

Other material -Material Group 1 assumed creepage distance 1.5 mm

 

For rectified dc voltage and FET maximum voltage use row for >300 < 600

Clearance distance 3.0 mm

Creepage Distance PWB 3.0mm

Material Group 1 3.0mm

 

Note that Table 4 uses the CTI Comparative Tracking Index BS5901:1980

For example, CTI > =600, means the material will withstand 600volts over a specified distance when exposed to 50 drops of contaminated water.

 

The solution normally used for this purpose is Solution A = 0.1% by mass of ammonium chloride added to distilled or or deionised water. The resistivity of this solution is 395 Ohm cms nominal.

 

Transformer

To determine clearance and creepage distances for the transformer we shall use:

 

EN 61588-1:2005 Safety of Power Transformers, Power Supplies, Reactors and similar products

This is the generic standard for transformers.

 

EN 61588_2-17:1998 Particular Requirements for transformers for SMPS

This is the standard amendment for switched mode power supplies, it is part 17 of the generic standard. It refers to information and tables within the generic standard. It states that Tables 13, C1, and D1 in EN 61588-1:2005 can be used at frequencies greater than 40KHz provided a multiplying factor of 1.1 is used. Clause 26.102

 

We are using material group II, pollution degree 2, working voltage 547V d.c, say 600V. Creepage and clearance distances are obtained from Table C.1, in Annex C of EN 61588-1:2005, for basic insulation as:

 

clearance = 5.5mm*1.1=6.05mm

 

creepage = 5.5mm*1.1= 6.05mm

 

PCB Material

We shall use FR4 as the PCB base material- note the FR stands for flame retardant and we shall use FR4 to reduce the risk of ignition under fault conditions. Note that the ability of a material to resist ignition is determined by the its flame retardant mechanism, which is defined by an index, such as FV-1, FH-1, etc. The V and H stand for vertical and horisontal. In Product X1, the PCBs are mounted vertically, and we shall specify FV-1 as the minimum flame retardant index.

 

The breakdown voltage of FR4 is typically 39KV/mm

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2.9 Component and Materials Specification

We are now in a position to make a first pass at the SMPS design. There is a lot of numerical detail involved, consequently we have carried out the design using a spreadsheet, u2-Calcs. The spreadsheet is protected but you can enter data into cells that require manual input. Editable cells are highlighted in green. The spreadsheet is read only, so if you do edit cells do not try and save the spreadsheet. If you wish to edit cells and save them take a copy of the workbook and download it to your computer.

 

Design equation developed in this unit are referenced in the spreadsheet, but numerous calculations are carried out in the spreadsheet that are not directly linked to equations, such as interim results. The spreadsheet has been prepared using symbolic notation so that all cells containing numerical data and/or formulae are named. To see the formula associated with a cell just click into it and the formula, in symbolic form, will appear in the formula bar.

Take care when using the spreadsheet that you use the correct units: SMPS design requires information from several engineering disciplines and they often have their own system of units. For example, much of the design information on SMPS transformers use Gauss (G) as the unit of flux density whilst the Tesla (T) is used in the modern system of international units. Note that 1T =10000G.

 

The design values we are principally interested in relate to voltage and current stresses.

 

We are using the SMPS in the discontinuous mode and to ensure this mode of operation in all products produced we have assumed a maximum duty cycle of 0.5. This value is used to select core inductances for the minimum a.c. input voltage, 110V minus 10%.

 

When the input voltage is 240V the SMPS controller automatically reduced the duty cycle to provide the correct output power, hence we are sure of remaining in the discontinuous mode for ranges of a.c. input voltage and output load current.

 

In general we use the minimum a.c. input voltage to determine worst case currents and the maximum a.c. input voltage stresses. R.M.S. currents are used for calculating power losses.

The initial design steps are listed below:

  1. Using eqn 2.1 the output power of the SMPS is calculated
  2. Set the SMPS switching frequency to 100KHz- from SMPS data sheet
  3. Set FET drain to source breakdown voltage to 700V- from SMPS data sheet
  4. Evaluate the FET maximum on current - eqn 2.2
  5. Set Dmax to 0.5
  6. Evaluate the secondary peak current at full load - eqn 2.6
  7. Evaluate the primary inductance LP
  8. Evaluate the secondary inductance LS

The design flow in the spreadsheet roughly follows the order in which data is entered and calculations are carried out.

 

Most of the equations and values in the spreadsheet are readily understood but the transformer insulation needs more explanation.

 

We shall start by considering creepage in more detail, as illustrated in Fig 2.15.

Figure 2.15 Creepage Distances

 

Figure 2.15 Creepage Distances

Fig 2.15 (a) shows the simple case of two conductors held at defined potentials separated by a defined distance. The shortest distance between the conductors is the creepage distance. Creepage, or tracking between conductors depends on the material separating them and any pollution that builds up on the surface. Because there is always a finite impedance between the tracks a small current will flow between them. This causes conductive deposits to be formed between the tracks due to electrolytic action. Over a period of time the resistance between the tracks decreases and may result in complete breakdown between them- the tracks arc over. Once this has happened the failed component must be replaced, or in the case of a low cost product, the product needs to be replaced. When arc over occurs large currents are likely to flow and the product must be protected against them. In addition the large currents may generate considerable heat in the location of the fault that could lead to a fire risk. To prevent fire flame retardant materials should be used for insulating materials.

 

Fig 2.15 (b) shows an IC in the vicinity of the high voltage track. The creepage distance has been reduced to Y2 and the creepage current now flows through the IC. The IC voltage is assumed to be virtually at GND potential (VDC<<V) from a creepage point of view. Remember current must always flow in complete loops.

 

Fig 2.15 (c) shows the effect of a "floating conductor" placed between the high voltage track and GND. The creepage path has been reduced to Y3+Y4. Note there is still a conduction path to allow the creepage current to flow in a complete loop. Some companies use PCB identifiers etched in the PCB copper- this is not a good idea, especially if the identifier is placed in the vicinity of high voltage tracks.

 

Note that the core of the SMPS is a "floating conductor"- we consider it to be at un undefined voltage- it is an equipotential region. We effectively assume it is a short circuit from the point of view of insulation.

 

Creepage between the primary and secondary winding is treated like the case of 2.15 (b). We assume all of the secondary winding is at the same potential, GND.

 

The transformer insulation is shown in Fig 2.16, note the creepage path between primary and secondary. We have chosen the shortest current path- the route for current flowing in from the ground connection back to the high voltage source, i.e. the primary winding. The creepage path between the primary and secondary windings is 2M.

Figure 2.16 Transformer Creepage and Insulation

 

Figure 2.16 Transformer Creepage and Insulation

The creepage distance obtained from the SMPS transformer standard was 6.05 mm, which makes M=3.025mm - we have specified 3mm.

The working voltage/turn for the primary winding is 7.48V (VPT). The insulation strength of enameled copper wire of 0.45mm diameter is 2300V (EN 60137-0-1:1998, Table 9).

The working voltage primary layers is 282V (Vpl). The insulation strength of polyester film is typically 7KV/mil so a single layer of film between primary layers is sufficient.

The working voltage between primary and secondary is 547V (Vps) so a single layer of insulation between primary and secondary is sufficient.

If an extra layer of insulation is used between layers the insulation type is upgraded to supplementary insulation, provided the insulation of any one layer has sufficient electric strength in the failure of another layer.

For voltages less than 600V the minimum thickness of insulation is 0.4mm EN61558-2-17:1997, clause 26.103

See EN61558-2-17:1997 for definitions of insulation types.

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2.10 PCB Layout

The various insulation levels are shown schematically in Fig 2.17. For insulation grading we have coloured all PCB traces and, where appropriate, components that are at the same approximate potential, the same. For example all the low voltage components are assumed to be at approximately the same potential as the protective earth and are coloured green. The FET drain potential traces have been coloured purple.

Figure 2.17 Schematic Showing Component and PCB Tracks Assumed Voltage Levels for Insulation Grading

 

Figure 2.17 Schematic Showing Component and PCB Tracks Assumed Voltage Levels for Insulation Grading

A representative PCB layout is shown in Fig 2.18- colours of PCB traces are the same as those used in Fig 2.18. All the high voltage components are shown in a high voltage zone and the low voltage components are shown in a low voltage zone. The isolating transformer bridges the two zones.

Figure 2.18 Illustrating PCB Insulation Layout Requirements

 

Figure 2.18 Illustrating PCB Insulation Layout Requirements

Referring to section 2.8, minimum creepage distances are as follows:

 

Mains and neutral - 1.5mm- this also applies to the PCB connector mains terminals.

 

Direct voltage with respect to the high voltage reference- 3.0mm

 

FET voltage with respect to the high voltage reference - 3.0mm

 

Minimum separation between any tracks/components in the high voltage zone and the low voltage zone - 3.0mm

 

Minimum clearances are the same as creepage distances, in this example.

 

PCB trace widths and component pin diameters are to be chosen for the correct current density, Jd.

 

In order to define the trace widths the copper thickness has to be chosen. Representative values of copper width for various copper weights/sq ft are shown in the spreadsheet: PCB section. The track widths, using 2 oz copper, for the high current tracks in the output circuitry are 18mm, whilst the track widths that carry the transformer primary current is 0.9mm. Note we have used RMS currents in these calculations.

 

Fig 2.19 shows the tracks that carry these high currents. The 18 mm tracks are shown in green : they will only be short and it may be worth considering an increase in the allowed current density for these tracks. Be careful when tracks are buried- the heat generated in them has to pass through solid dielectric to escape to the atmosphere. The 0.9 mm tracks are shown in red- again be careful when tracks change layers and make sure via dimensions are sufficient to carry the current.

Figure 2.19 Track Widths for some High Current Tracks

Unfortunately it is necessary to calculate the current in all the high current traces to determine the trace widths.

 

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2.11 Case and Power Connections

In this section we shall consider the case and power connections to the product, including the power cord.

 

The Case

There are two major considerations for the case, which is made of metal:

  1. There should be sufficient clearance between the case and any exposed electrical conductors that are at a high potential
  2. The case should be connected to the protective earth of the power supply securely and reliably with a low resistance connection.

The clearance distance is 3.0 mm for both a.c. and direct voltage, in our example. We have assumed the PCB card nearest the side of the case is the power supply card. The minimum clearance between high voltage components and the side of the case should be 3.0 mm, but it would be sensible to increase this to say 6.0 mm. This effectively doubles the insulation strength. Alternatively, an insulating sheet could be adhered to the inside of the case, for example.

Figure 2.20 Illustrating Clearances between PCBs and the Case

 

Figure 2.20 Illustrating Clearances between PCBs and the Case

Note that the PCB cards should be secure- that is they must not be allowed to move in normal operation or if the product receives a mechanical shock. The PCBs would probably be fixed in position by guides that are securely fixed to the bracket holding the PCB connectors. This ensures the distance between the case and high voltage conductors is controlled. Note that clearances must be adhered to for the PCB next to the power supply PCB.

 

Clearance, creepage distances and current ratings must also be applied to the PCB connector. Fig 2.21 shows some examples of the problems encountered and possible solutions.

Figure 2.21 Connector PCB Pad Creepage Distances

 

Figure 2.21 Connector PCB Pad Creepage Distances

The live and neutral connector pins have been connected in parallel to increase the current capacity- note that the connector live and neutral pins on the PCB back plane must be connected together, as well as the connector live and neutral PADS on the SMPS PCB.

 

Creepage distances between the connector PCB pads have been effectively increased by interspersing floating PCB connector pads, coloured blue, between high voltage pads and high voltage pads and low voltage pads. Note that the creepage distance CD= CD1 + CD2.

 

The best solution is to use a connector that has the correct current capacity, clearance distances and creepage distances, if one is available and it will fit into the space available.

 

We shall now consider the mains connector and the protective earth, which are shown in section in Fig 2.22.

Figure 2.22 The Case Mains Connector and Protective Earth

 

Figure 2.22 The Case Mains Connector and Protective Earth

The connector mounted on the case should be a male type and the connector that engages with it should be a female type to prevent the user being exposed to live mains. The protective earth is securely fixed to the case with a screw that is tightened to a specified torque. The serrated washer cuts into the case material to ensure good contact is made between the case and the earth, even if the case material is prone to oxidisation. The solder tag is held in position with a shakeproof washer, which again cuts into the solder tag material and also prevents the nut becoming loose if the product is subjected to mechanical shock. The protective earth cable must be correctly rated and it should be kept short: in our case it has been soldered to the protective earth pin on the connector and earth solder tag. It is good practice to cover exposed connections with insulating sleeving of the correct colour, i.e. green or green and yellow for earth.

 

The quality of the earth connection is defined as a resistance and it may be measured with a circuit as shown in Fig 2.23.

Figure 2.23 Circuit for Measuring the Resistance of the Protective Earth Connection

 

Figure 2.23 Circuit for Measuring the Resistance of the Protective Earth Connection

A current I is injected into the earth solder tag that flows to the case. The small voltage across the solder tag to case is measured which allows the resistance of the protective earth to be determined.

Consistency of the protective earth resistance value from product to product may be ensured by using a torque spanner, set to give the required resistance.

 

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2.12 Unit Summary

In this unit we have considered the design of a switched mode power supply of the flyback type operating in the discontinuous mode to illustrate several key aspects of designing electronic products to comply with the Low Voltage Directive. We could have considered much simpler examples to illustrate the design principles pertaining to LVD but the SMPS presents several real challenges to the designer of electronic products, and has been chosen for this reason.

 

An important principle, implied in the presentation of this unit, is that designers should understand the circuits that they are developing. This enables them to appreciate the reasons for the design approach and decisions they are taking and, importantly, allows them to design for situations outside their experience. Rules of thumb have been avoided, except in a few cases, and design criteria have been traced back to the relevant standards and directives, where appropriate.

 

Detailed design equations that allow the circuit and the product to be designed to comply with the Low Voltage Directive have been developed. Several manufacturers have produced detailed design guides for their SMPS devices, but we have steered clear of considering designs using specific integrated circuits.

 

Important design criteria, such as pollution degree, clearance, creepage and insulation levels have been specified using the relevant standards and the product requirements.

 

Numerical calculations have been presented in a spreadsheet and the user may alter values, highlighted in green, to quickly assess design changes.

 

Designing for LVD encompasses more than just designing to withstand voltage stress, current ratings are also important, and issues relating to the current capacity of conductors have been addressed.

 

Practical design considerations at the PCB level and product level have also been covered.

 

It is intended that the skills and knowledge developed in this unit will enable the designer to apply them to a wide range LVD design problems.

Key Information

The design presented in this unit is a first pass design- it is not complete.

 

We have not specified a fuse, we have not decided if the reference point of the low voltage circuitry should be connected to the protective earth, we have not considered the effects of mains borne high voltage surges, we have not considered harmonics and we have not considered voltage dips. We shall consider all of these in subsequent units and we shall use the SMPS as a running design example to illustrate them. This allows us to integrate the various design criteria for both LVD and EMC for the product as a whole.

 

The hard work we done in understanding the SMPS will be useful in several of the units that follow.

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2.13 Standards referenced used in this Unit, Useful Information & Useful Links

EN61010-1:2001 Safety Requirements for electrical equipment for easement, control and laboratory use

 

EN 61588-1:2005 Safety of Power Transformers, Power Supplies, Reactors and similar products

 

EN 61588_2-17:1998 Particular Requirements for transformers for SMPS

 

BS5901:1980 CTI Comparative Tracking Index

 

EN 60137-0-1:1998: Specifications for particular types of winding wires

 

EN60695-1-1:2000 Fire Harzard Testing

 

BS 4584 103.1, 103.2 and 103.3: Metal Clad Base Materials for Printed Wiring Boards

 

BS 6221-1 to BS 6221-25: Standards for all aspects of PCBs

Spreadsheet: u2-Calcs.

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Updated: 18/07/07 RJH

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