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PCB Design and Electromagnetic Radiation

In this topic we shall introduce and discuss PCB design techniques that reduce product susceptibility to external electromagnetic radiation. We shall also cover design techniques that that reduce product radiated emissions.

The CE standards relating to both radiated emissions and susceptibility to external radiation will be covered and testing methods will be outlined.

Many of the diagrams used in this topic are taken from the text:

 

Ref 1

EMC for Printed Circuit Boards

Basic and Advanced design and layout techniques

Keith Armstrong Eur Ing C. Eng MIEE MIEEE

Published by: Nutwood UK Limited

ISBN: 978-0-9555118-0-6

Ref:1

 

This book is on the suggested reading list for AMI 4966 Design for EMC and LVD and AMI4815 Signal Integrity and EMC.

We shall start by introducing several principles that underpin the PCB design techniques used in this topic.

Contents

 

Authors

Author, Ron HoodRon Hood

Ron has many years industrial experience as an electronic development engineer working for large companies such as GEC and several smaller companies throughout the UK. He has developed industrial electronic systems, instrumentation systems and control systems for both military and industrial applications. As Technical Director he was responsible for products that included customised ASIC solutions and microprocessors, and for liaison with manufacturers in the Far East. For the last ten years he has run a design consultancy providing hardware and software solutions to clients that include large and small companies.
Ron has more than ten years experience working with higher education, lecturing in electronics and related subjects at honours degree and MSc level and supervising projects for MSc and PhD degrees.

Author, Keith ArmstrongKeith Armstrong

keith.armstrong@cherryclough.com

www.cherryclough.com

Keith graduated from Imperial College, London, in 1972 with an Honours Degree in Electrical Engineering, has been a member of the IEE (now the IET) since 1977, a UK Chartered Engineer since 1978, and a Group 1 European Engineer since 1988.

Cherry Clough Consultants was started by Keith in 1990 to help companies reduce costs, timescales and warranty costs whilst also complying with the EMC Directive and other regulations world-wide.

Keith has presented many papers, demonstrations, and training courses on EMC, and on EMC for Functional Safety, worldwide, and has also written many articles on these topics.

He teaches a module on EMC for the University of Manchester’s MSc course on Sensors and Electronic Instrumentation.

He chairs the IET’s Working Group on “EMC and Functional Safety”, and is the UK’s authorized representative on the IEC teams working on:
IEC 61000-1-2 (EMC & Functional Safety, MT15), and
IEC 60601-1-2 (EMC for Medical Devices, MT23).

 

 

1.0 Underpinning Principles of PCB Design Techniques

The following principles may be used as a starting point for designing PCBs that have good EMC performance:

 

The commercial drive for products that operate at higher and higher speeds poses real problems for EMC.

Higher operating speeds mean that products are susceptible to interference over wider frequency bands.

High frequency operation demands reduced logic levels to achieve fast transition times. This reduces noise gate and system immunity.

Operating at high frequency inevitably increases power dissipation and reduced supply voltage logic levels are accompanied by an increase in supply current.

The increase in product operating speeds and product complexity increases product radiated emissions significantly.

In the sections that follow we shall illustrate the use of the above principles using practical examples and, where possible, examples from real PCBs.

 

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2.0 The Effects of High Speed Operation on EMC

In this section we shall consider the effects of high speed operation of digital systems on EMC.

Fig 1 shows an idealised clock signal waveform used in a digital system. Note that the mark/space ratio in the figure is not 1:1. This is the practical situation: the effects of tolerances on clock circuit performance is that there is a unit to unit variation of clock mark/space ratio. The harmonic content increases significantly when the mark/space ratio departs from 1:1.

Figure 1 Digital Clock Waveform: unequal mark/space ratio

 

Figure 1 Digital Clock Waveform: unequal mark/space ratio

$\begin{gathered} {\text{The coefficient of the nth harmonic is:}} \hfill \\ a_n = \frac{1} {{T_P }}\int\limits_{\frac{{ - w}} {2}}^{\frac{w} {2}} {V\cos n\left( {\frac{{2\pi nt}} {{T_P }}} \right)} dt....................................................1 \hfill \\ {\text{Where }}T_P {\text{ is the periodic time of the clock signal}} \hfill \\ \hfill \\ {\text{The expression for the coefficient of the nth harmonic is:}} \hfill \\ \hfill \\ a_n = 2Vwf_P \left[ {\frac{{\sin \left( {n\pi wf_P } \right)}} {{n\pi wf_P }}} \right].......................................................2 \hfill \\ \hfill \\ {\text{Where }}f_P {\text{ }} = 1/Tp{\text{ and is the clock frequency}} \hfill \\ \end{gathered} $

The harmonic content of a clock signal with a mark space ratio of 1:1 is shown in Fig 2 (a).

 

Figure 2 Clock Signal Harmonic Content

 

Figure 2 Clock Signal Harmonic Content

The harmonic content of a clock signal with a mark/space ration of 0.8, that is THI/TLO =0.8, is shown in Fig 2 (b). Note that the harmonic content is increased significantly. Negative values of the harmonics indicate a phase shift of 180 degrees.

The plots in Fig 2 have been obtained using the spreadsheet excel_006. We suggest you use this spreadsheet to see the effects of varying key waveform parameters.

Levels of electromagnetic radiation from a single PCB trace increase with:

Reducing any, or all, of the above parameters reduces levels of radiation and hence improves EMC performance and makes EMC compliance easier.

In high speed digital systems the important parameters that control switching speed are gate output current, load capacitance and the voltage swing across the load capacitance during switching. The expression for the rise time of a gate output is given in equation 3. We have assumed a linear rate of rise of voltage, which is equivalent to assuming a constant gate output current.

$\begin{gathered} i = C\frac{{dv}} {{dt}} \hfill \\ \hfill \\ i \approx C\frac{{V_{DD} }} {{t_R }}{\text{ }}\therefore {\text{ }}t_R = C\frac{{V_{DD} }} {i}............................................................3 \hfill \\ \end{gathered} $

We can see that switching time is directly proportional to supply voltage. To achieve high speed operation integrated circuit manufacturers produce logic families with reduced voltage supplies. Unfortunately this also reduces gate noise immunity. The relationship between noise immunity and supply voltage is shown in Fig 3.

Figure 3 Illustrating the Reduction in Noise Immunity as a Function of Supply Voltage

 

Figure 3 Illustrating the Reduction in Noise Immunity as a Function of Supply Voltage

Fig 3(a) shows a single NAND gate with a supply voltage of VDD. Figures 3 (b), (c) and (d) show the relationship between supply voltage and noise immunity. We have assumed that the gate threshold voltage range is 0.3VDD to 0.7VDD.

 

Reducing system supply voltage makes our products more susceptible to external radiation.

 

Power consumption also increases with increasing operating frequency.

 

$\begin{gathered} {\text{For a single CMOS gate driving a capacitive load the energy supplied to the load}} \hfill \\ {\text{when the gate switches from LO to HI is:}} \hfill \\ \hfill \\ E = \frac{1} {2}C_S V_{DD}^2 \hfill \\ {\text{The same amount of energy is dissipated in the gate output transistors during this}} \hfill \\ {\text{transition}} \hfill \\ \hfill \\ {\text{When the gate switches from HI to LO the energy stored in the load capacitance is}} \hfill \\ {\text{dissipated in the gate output transistors}} \hfill \\ \hfill \\ {\text{The total energy dissipated in the gate output tansistors on each signal pulse is:}} \hfill \\ E_T = 2 \times \frac{1} {2}C_S V_{DD}^2 = C_S V_{DD}^2 \hfill \\ {\text{The aveage power dissipated in the gate, assuming it switches on each clock pulse is:}} \hfill \\ P_{AVE} = \frac{{C_S V_{DD}^2 }} {{T_P }} = C_S V_{DD}^2 f.......................................................................4 \hfill \\ \hfill \\ \end{gathered} $

Equation 4 shows that power consumption increases linearly with frequency. Increased power consumption poses problems for compliance with several EMC standards, in particular harmonic emissions into the mains supply.

 

To improve EMC performance:

Using logic gates with "long" transition times means that interference from radiation at higher frequencies does not degrade performance: gate response times are too long for them to react.

 

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3.0 Partitioning at Product Level

In this topic we are mainly concerned with the effects of electromagnetic radiation on PCB design. However many products use several PCBs and the first stage of partitioning should be at product level.

There is a strong temptation to partition according to function. For example a product that acquires data from analogue and digital sensors, process the data prior to displaying it, uses the processed data for control purposes and then transmits the data to a central monitoring system could be partioned according to function as follows:

 

Assuming the analogue and digital inputs are relatively slow the circuitry associated with them could be made to operate at a speed that is sufficient to sample the input data to the required level of accuracy

Power supply voltages could be chosen to give a high level of noise immunity, for example the 4000 CMOS series can work up to a voltage of 15 volts, with a corresponding noise immunity of 4.5 volts. Response times of the 4000 series would ensure that interference occurring at frequencies above about 10MHz would have no effect on board performance.

Each input board could have its own local microprocessor operating at a clock speed fast enough to satisfy product performance requirements.The processor can be simple and inexpensive.

Finally power requirements for the low speed input board are likely to be modest and a locally mounted power supply would ensure that coupling between boards via power supplies is reduced significantly.

A similar approach could be used for the output (control) boards. Again operating speed requirements are likely to be slow. Care should be exercised when determining output power requirements.

Assuming the main processing board needs to operate at high speed because it has to process data from several input boards and send data to several output boards, voltage supply levels and clock speed would be chosen to meet product performance requirements. A switched mode power supply could be used- the main processing board is likely to consume most power.

Intercommunication between the various boards and between the product and the external monitoring system could be integrated into the backplane. Techniques are available that allow high speed communication between boards that are very robust.

Product partitioning described above is shown in Fig 4.

Figure 4 Example of Product Partitioning taking into Account EMC and Signal Integrity Requirements

 

<h3>Figure 4 Example of Product Partitioning taking into Account EMC and Signal Integrity Requirements</h3> <p> </p>

The partioning shown in Fig 4 is illustrative only: more detailed considerations would be required when partitioning a real product.

 

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4.0 PCB Layout and Segregation

In this section we shall consider the principles of partitioning at PCB level. Figure 5 shows a single PCB partitioned into zones. The purpose of partitioning is to separate circuits into zones so that they do not interfere with each other.

Figure 5 An Example of Segregation on a Single PCB

 

Figure 5 An Example of Segregation on a Single PCB

Only essential interconnects are made between zones and provision is made for suppressing or filtering these at the edges of zones. If suppression is found not to be necessary when the prototype PCB is evaluated suppression components can be omitted from production models.

When the PCB is made ready for production or when it is first revised the zero ohm links can be replaced with short tracks without degrading EMC performance.

Interconnects between zones should not cross other zones.

The analogue zone in Figure 5 has been split into two zones, a sensitive zone which is close to the PCB edge and a zone where the analogue signals may have been raised to a relatively high level.

The digital zone is also split into two zones, a high speed zone and a slower zone. Note that the high speed zone is positioned towards the centre of the digital zone so that it does not interfere with the analogue zone and is not interfered with by the switch mode power supply.

A single 0V reference plane is used. it has not been split into analogue and digital "grounds".

Power supply planes have not been shown in Figure 5, we shall deal with these later in the topic.

Segregation does not only reduce internal interference, if external radiated interference enters a zone it may be conducted into other zones. Segregation and suppression reduces this type of interference.

Filtering and protection of the PCB external cables should be done in the filter zone and screened cables should also be bonded to the PCB in this zone.

 

 

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5.0 PCB Stackup

In this section we shall consider multilayer printed circuit boards and in particular how the PCB arrangement of the layers affects EMC performance.

The PCB has evolved from single sided boards, through double sided boards, then to 4 layer boards, etc. At the time of writing this topic PCBs with 12 layers are common and boards with higher layer counts are possible.

Traditionally PCB designers add layers to a PCB because of space limitations, that is there is not enough board area for the interconnects or it is impossible to route some interconnects without shorting others.

The use of signal reference planes and power supply planes, however, really produce improved signal integrity (SI) and EMC performance.

The arrangement of PCB planes is commonly referred to as PCB stackup. We shall now consider several PCB stakup arrangements and indicate their benefits for EMC performance.

Important information

Factors that influence stackup other than electrical considerations are board mechanical strength, thermal stability and vibration, etc. We shall only consider thermal stability and electrical performance in this section.

We shall start by considering PCB thermal stability. Probably the most stressful thermal situation a PCB is subjected to is when components are soldered to it during the assembly process. PCBs are thin, usually about 1.5mm thick and typically they are made up of several layers of copper and insulating material, such as FR4.

If the arrangement of copper layers on the PCB is not symmetrical about the PCB centre line it is likely the PCB will warp because of stresses caused by differential temperature effects, during the soldering process.

Symmetry is realised by "balancing the copper layers" about the PCB centre line as illustrated in Fig 6, which shows the edge view of a fragment of an 8 layer board.

Figure 6 Illustrating Copper Balance on a PCB

 

 

Figure 6 Illustrating Copper Balance on a PCB

The amount of copper on layers 1 and 8 is to be the same and the distance of both layers from the PCB centre line is the same. This is equivalent to taking moments of the layers about the PCB centre line. The same principle may be applied to the other layers:

 

$\begin{gathered} {\text{If }}Wn{\text{ = the weight of a layer and }}Xn{\text{ = the distance of the layer from the PCB centre line}} \hfill \\ \hfill \\ W_1 \times X_1 = W_8 \times X_8 \hfill \\ \hfill \\ W_2 \times X_2 = W_7 \times X_7 \hfill \\ \hfill \\ W_3 \times X_3 = W_6 \times X_6 \hfill \\ \hfill \\ W_4 \times X_4 = W_5 \times X_5 \hfill \\ \hfill \\ {\text{In practice the distances }}X1{\text{ }} = {\text{ }}X8,{\text{ }}X2{\text{ }} = {\text{ }}X7{\text{, etc}}{\text{. so that }}W1 = {\text{ }}W8,{\text{ }}W2{\text{ = }}W7{\text{, etc}} \hfill \\ \hfill \\ \end{gathered} $

The weight of copper on a layer is the weight of the traces, not the weight of the layer before etching.

Note that layers do not have to be evenly distributed about the PCB centre line and as we shall see they should not be if good EMC performance is to be realised.

Unused copper must not be left on PCB layers to achieve copper balance as this degrades EMC performance.

The number of layers in a PCB stackup is normally an even number to allow copper balance to be achieved.

We shall now consider some examples of PCB stackups.

Figure 7 shows a traditional 4 layer PCB stackup.

Components are not shown but they would normally be mounted on the surface closest to the 0V plane.

Cross talk between the interconnects on opposite sides of the PCB is reduced by the conductive planes.

Figure 7 Traditional 4 Layer Stackup 7Ci

Figure 7 Traditional 4 Layer Stackup

 

  1. Microstrip signal traces
  2. The 0V signal reference plane and power supply 0V
  3. Power supply plane
  4. Microstrip signal traces

Figure 8 shows a 4 layer PCB stakup with the signal and reference planes on the outer surfaces.

The intention is to use the planes as shields for the interconnects. However, the plane on the component side would be heavily perforated and shielding effectiveness is significantly reduced.

The the separation of the reference planes decreases self capacitance and increases self inductance which increases supply impedance to switching noise and interference.

Figure 8 A 4Layer Stackup Planes on Outside 7C ii

Figure 8 A 4Layer Stackup Planes on Outside

 

  1. 0V signal reference plane and 0V power supply plane
  2. Offset stripline traces
  3. Offset stripline routed orthogonal to the traces on layer 3 to reduce crosstalk
  4. Power plane

The stackup shown in Fig 8 is not recommended.

 

Fig 9 shows a 4 layer stackup using unequal layer spacings. The 0V reference plane and the power supply are close together to give high inter-plane capacitance and low inter-plane inductance which equates to low power supply impedance to switching transients.

Figure 9 A 4 Layer Stackup using an Embedded Stack 7Di

 

Figure 9 A 4 Layer Stackup using an Embedded Stack

Unfortunately the signal lines are now relatively far from the reference planes which makes them susceptible to interference. Also the control of trace impedance, using transmission line techniques is degraded.

Figure 10 shows a low cost 4 layer PCB recommended by Intel for Personal Computer motherboards in the 1990s.

Figure 10 Intel's Recommendation for Low Cost 4 Layer PCB Motherboards in the 1990s 7D ii

 

Figure 10 Intel's Recommendation for Low Cost 4 Layer PCB Motherboards in the 1990s

The power and 0V reference plane are close to the outer layer of the PCB which gives good control of signal traces for signal integrity and EMC. However, the 0v and power planes are relatively far apart which is not conducive to low power supply impedance. This arrangement would not be suitable for high speed digital applications operating in the high megahertz range and above.

In order to obtain both good signal integrity and EMC performance, particularly for high speed, high frequency systems, it is necessary increase the number of PCB layers.

Layers should be positioned taking into account the following:

Figure 11 shows a 6 layer board which employs some of the principles listed above. Note the use of embedded microstrips on layers 2 and 5 for long interconnects running orthogonally to microstrips on layers 1 and 6, to reduce crosstalk. Power supply and reference planes are close together to give low power supply impedance.

Figure 11 A 6 Layer Board

 

Figure 11 A 6 Layer Board

Fig 12 shows an 8 layer board that uses multiple 0V and power planes.

The stackup is symmetrical about the PCB centre line.

Layer 2 is a 0V reference planes and is close to layer 3 , its associated power plane, to provide low power supply impedance.

Layer 1 is close to layer 2 which allows signal traces to be defined and controlled.

Layer 4 uses embedded offset striplines which are screened by the power supply planes.

Figure 12 An 8 Layer Board 7J

 

Figure 12 An 8 Layer Board

The 0V planes in Fig 12 should be connected together and so should the power planes, probably in the PCB filter zone, close to the edge connector.

The stakup shown in Fig 12 satisfies many of the requirements for both SI and EMC performance. Additional layers would be used if more area is required for routing traces. When more layer are introduced care should be taken to include 0V reference planes for them and to maintain copper balance.

 

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6.0 European Standards Relating to Radiated Emissions and Susceptibility

In this section we shall consider some European Standards that are applicable to Electromagnetic Radiation.

 

The standards pertaining to electromagnetic radiation we shall use in this topic are:

 

6.1 EN55022:2006 Information Technology Equipment- Radio disturbance characteristics- Limits and methods of measurement.

Figure 13 shows the basic test setup for measuring emissions radiated by our product.

Figure 13 Radiated Emission Limits Basic Test Setup

 

Figure 13 Radiated Emission Limits Basic Test Setup

Our product is placed 10m away from an RF measuring system and the level of radiation emitted by it is detected by an antenna/radio receiver system. Note that the levels of radiation set by the standard are small and are expressed in dBuV.

The frequency range used in the test is from 30MHz to 1 GHz.

There are two classes of equipment defined in the standard, class A ITE, and class B ITE.

Class A limits as defined by the standard are shown in Table 1 (Table 5 in the standard).

Table 1 (Table 5 in EN55022:2006) Limits for Radiated Disturbances of Class A ITE Equipment at a measuring Distance of 10m)

Frequency Range

MHz

Quasis-Peak Limits

dB(uV/m)
30 to 230
40
230 to 1000
47

NOTE 1 The lower transition frequency shall apply at the transition frequency

NOTE 2 Additional provisions may be required for cases where interference occurs

Table 2, (Table 6 in the standard), shows the limits for class B equipment.

Table 2 (Table 6 in EN55022:2006) Limits for Radiated Disturbances of Class B ITE Equipment at a measuring Distance of 10m)

Frequency Range

MHz

Quasis-Peak Limits

dB(uV/m)
30 to 230
30
230 to 1000
37

NOTE 1 The lower transition frequency shall apply at the transition frequency

NOTE 2 Additional provisions may be required for cases where interference occurs

Tables 1 and 2 are illustrated in Fig 14, which shows the limits for both standards plotted against frequency.

Figure 14 RF Immunity Standards in Graphical Form for IT Equipment

 

Figure 14 RF Immunity Standards in Graphical Form for IT Equipment

6.2 EN61000-4-3:2006 Testing and Measurement Techniques Radiated radio-frequency electromagnetic immunity tests

Figure 15 shows the basic test setup for measuring the immunity, i.e. the susceptibility of products, to electromagnetic radiation.

Figure 15 Figure 15 Immunity to Radiation Basic Test Setup

 

Figure 15 Figure 15 Immunity to Radiation Basic Test Setup

Our product is placed 10m away from an RF transmitter and subjected to fairly high levels of RF interference over the frequency range of 80MHz to 1GHz.

 

Table 3 (Table 1 in the standard), shows the levels of electromagnetic radiation defined in the standard for different classes of equipment.

Table 3(Table 1 in EN61000-4-2) Test Levels Related to general purpose, digital radio telephones and other RF equipment
Level

Test Field Strength

V/m
1
1
2
3
3
10
4
30
x
Special
NOTE x is an open test level and the associated field strength may be any value. This level may be given in the product standard

Annex E in the standard suggests which types of equipment may be covered by the different classes, that is which field strength to use in the test.

 

Note that EN61000-4-6 Immunity to RF Fields covers the frequency range 150KHz to 80 MHz.

The RF transmitted signal used in the tests is amplitude modulated to more closely represent the real, practical situation.

 

Fig 16 (Fig 1in EN61000-4-2) shows test modulated waveform defined in the standard.

Figure 16 RF Radiation Modulated Waveform (Figure 1 in EN61000-4-2)

 

Figure 16 RF Radiation Modulated Waveform (Figure 1 in EN61000-4-2)

 

 

 

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7.0 PCB RF Design Techniques

Before we consider PCB design techniques we shall remind ourselves of a few important facts associated with electromagnetic radiation.

 

$\begin{gathered} {\text{The speed of propagation of an electromagnetic wave in a dielectric is:}} \hfill \\ \hfill \\ u = \frac{c} {{\sqrt {\varepsilon r} }} \hfill \\ {\text{where c = the speed of light in free space = 300}} \times 10^6 m/s \hfill \\ \hfill \\ \varepsilon r = {\text{ the relative permittivity of the dielectric, about 4 for FR4}} \hfill \\ \hfill \\ {\text{So the speed of progation along a PCB }}{\text{trace is about 150}} \times 10^6 m/s \hfill \\ \hfill \\ {\text{The velocity of propagation along a track is }}u{\text{ }} = {\text{ }}\frac{L} {{tpd}} \hfill \\ {\text{where }}L{\text{ = length of the track and }}tpd{\text{ = the propagtion delay along the track}} \hfill \\ \hfill \\ tpd{\text{ }} = {\text{ }}\frac{L} {u} = {\text{ }}\frac{1} {{150 \times 10^6 }}{\text{ for a track length of 1 metre}} \hfill \\ \hfill \\ {\text{For FR4, }}tpd \approx 6.67nS/m \hfill \\ \hfill \\ {\text{For a signal with a rise time }}t_R {\text{, the spacial extent of the signal wavefront on a PCB }}{\text{track is}} \hfill \\ \hfill \\ x_S = ut_R \hfill \\ \hfill \\ {\text{for a signal with a rise time of 1nS, this is 150mm}} \hfill \\ \hfill \\ {\text{PCB }}{\text{traces about this length and longer should be transmission lines and correctly terminated}}{\text{. }} \hfill \\ \end{gathered} $

$\begin{gathered} {\text{The intrinsic impedance of free space is }}Zi{\text{ }} = \sqrt {\frac{{\mu _0 }} {{\varepsilon _0 }}} {\text{ }} = 377\Omega \hfill \\ \hfill \\ {\text{The intrinsic impedance of a dielectric is }}Zd{\text{ }} = {\text{ }}\frac{{Zi}} {{\sqrt {\varepsilon r} }} \hfill \\ \hfill \\ {\text{For FR4 with }}\varepsilon r{\text{ }} \approx {\text{ }}4,{\text{ }}Zd{\text{ }} = {\text{ }}\frac{{377}} {2}{\text{ }} = {\text{ }}188.5\Omega \hfill \\ \hfill \\ {\text{This means that the characteristic impedance of transmission lines on a PCB must be}} \hfill \\ {\text{less than }}188\Omega {\text{ and in practice is limited to about 130}}\Omega {\text{ }} \hfill \\ \hfill \\ \end{gathered} $

 

 

$\begin{gathered} {\text{The voltage picked up in a PCB }}{\text{trace when it intercepts and em wave with its electric}} \hfill \\ {\text{vector }}E{\text{ orientated along its length }}L{\text{ is:}} \hfill \\ v = EL{\text{ }} \hfill \\ \hfill \\ {\text{For a PCB trace 100mm long that is subjected to an em wave of intensity }}E{\text{ }} = 10V/m{\text{, the}} \hfill \\ {\text{induced voltage is }}10V/m \times 0.1m = 1{\text{ }}volt. \hfill \\ \hfill \\ {\text{This is significant in comparison with the noise immunity of a CMOS digital gate}}{\text{.}} \hfill \\ \end{gathered} $

 

Finally, PCB traces act as unintentional antennas which radiate em energy into space. The Electric field associated with this radiation is inversely proportional to distance.

 

We may consider individual PCB traces as antennas, or we may consider the current loops PCB traces form to act as loop antennas: remember current always flows in loops.

 

Fig 17 shows the electric field at a point P, distance r from a fragment of a PCB trace carrying a sinusoidal current I. The length of the trace is L.

Figure 17 The Electric Field Emitted by a Short PCB Trace in the x-y Plane

 

Figure 17 The Electric Field Emitted by a Short PCB Trace in the x-y Plane

 

\[ \begin{gathered} {\text{The value of the electric field emitted by the trace at point P , for }}\theta {\text{ = 90}}^\circ {\text{ is:}} \hfill \\ E_\theta = IL\frac{f} {{c^2 2\varepsilon _0 r}} \hfill \\ \hfill \\ {\text{If we assue }}I = {\text{ }}1mA,{\text{ }}f = {\text{ }}100MHz{\text{ and the length of the trace }}L = {\text{ }}10mm \hfill \\ \hfill \\ E_\theta = \frac{{1 \times 10^{ - 3} \times 0.01 \times 100^6 }} {{\left( {300 \times 10^6 } \right)^2 \times 2 \times 8.85 \times 10^{ - 12} \times 10}} \hfill \\ E_\theta = 141\mu V/m \hfill \\ \hfill \\ {\text{The Class B ITE Standard allows }}30dB\mu V/m,{\text{ which corresponds to about }}32\mu V/m{\text{ }} \hfill \\ \hfill \\ {\text{The limits imposed by the standard would be exceeded}} \hfill \\ \hfill \\ {\text{Note that a 1}}{\text{.8V CMOS driving a 50}}\Omega {\text{ load sources a current of about 36mA}} \hfill \\ \end{gathered} \]

If our product emitted this level of radiation, 141uV/m, from a single short PCB trace, it would not pass the EMC compliance test.

In most instances the antennas on a PCB are part of circuit, or loop, and all of the loop radiates electromagnetic energy. It is possible to represent the loop formed by the circuit as a loop antenna.

Figure 18 (a) shows the radiation from a part of a PCB loop carrying a current I. The contribution of both current elements tend to cancel at a point P, some distance from the loop. For example, if the current is sinusoidal the contribution to the em field from element x is opposite in direction to that produced by element y, they tend to cancel. The fields produced by the elements at point P differ in both phase and amplitude. If the distance between the traces is decreased cancellation is more complete and the radiated field at P is reduced,

To reduce radiation from PCB loop try and minimise loop area. Using a signal trace over a conductive reference plane gives almost perfect cancellation of em radiation.

Figure 18 EM Radiation and PCB Circuit Loops

 

Figure 18 EM Radiation and PCB Circuit Loops

Figure 18 (b) shows an em wave incident on two PCB traces. E1 and E2 will differ in both amplitude and phase because of the trace separation: E1 > E2 and E2 lags E1. The difference causes a differential interference signal in the traces that degrades signal integrity. Reducing the separation between the traces, Fig 18 (b), reduces the differential interference produced by the wave. Fig 18 (c) shows the two traces running over each other on the opposite sided of a thin layer of PCB material like FR4. Cancellation is almost perfect.

The separation between the traces should be much less than the wavelength of the interfering em wave. In Fig 18(c) the trace separation would be several mils and cancellation would be almost perfect.

EM radiation is normally considered to be common mode interference, but finite trace separation converts common mode interference to differential mode interference, which degrades signal integrity.

 

Conversion of Differential Mode to Common Mode

Note: radiation from circuits and traces within our product may be coupled to the cables leaving our product as common mode radio frequency signals. These cause RF common mode currents to flow in the external cables, which act as very effective, but unwanted, antennas. This type of radiated interference may cause our product to fail RF emissions tests.

Any unwanted RF signal currents flowing through the common mode impedance of our product my also cause unwanted common mode currents to flow in cables leaving our product, which will act as effective antennas.

We shall now discuss a number of techniques that improve the EMC performance of PCBs.

Fig 19 (a) shows an integrated circuit and a decoupling capacitor mounted on a small fragment of a PCB. The VSS pin of the IC is connected to the 0V plane using a "blind via in pad", which gives the shortest possible connection length and minimum inductance. The IC VDD pin is connected to the VDD plane in a similar fashion. Ideally the diameter of the via holes should be small.

The use of blind vias means that perforations of the PCB conductive planes are minimised, which improves screening and minimizes the distortion of current flow.

The decoupling capacitor is placed close the IC VDD pin and its terminals are connected to the VDD plane and the 0V plane using blind vias.

Figure 19 Connecting to VDD and 0V PCB Planes

Figure 19 Connecting to VDD and 0V PCB Planes

Fig 19 (b) shows the plan view of the IC to show the via in pad connection, for both VDD and VSS.

Fig 19 (c) shows the plan view of the decoupling capacitor mounted on the PCB. The PCB pads for the capacitor have a relatively large area and each is bonded to the conductive planes using two vias in each pad. The large area reduces inductance and the vias bond the capacitor pads to the planes effectively, that is they have low inductance.

The PCB pads are shown in more detail in Fig 19 (d).

Fig 20 (a) shows the plan view of a 0V plane and its associated VDD plane. The VDD plane is inset to the 0V plane around the edges of the PCB. The edge view of a fragment of the PCB is shown in Fig 20 (b).

Figure 20 PCB VDD and 0V Plane Inset

 

Figure 20 PCB VDD and 0V Plane Inset

Fig 20 (c) shows that fringing of both for both the signal trace and the VDD plane are kept largely inside the dimensions of the PCB, provided the width of the inset is much greater than the plane separation. Only fringing associated with the electric field is shown in Fig 20 (c), but the same argument may be used for the magnetic fields associated with currents.

Detailed considerations of power plane integrity may be found at:

 

AMI4823 Design for Signal Integrity Unit 6 Power Integrity

 

Connections between signal lines and planes have a major effect on PCB EMC performance. Fig 21 shows some examples of microvias used in High Density Interconnect Technology (HDI). Micro vias may connect surface traces to buried layers or they may be buried within the PCB stackup. Blind microvias only interconnect the traces and planes they are supposed to and they do not cause excessive perforation of planes on different layers.

Figure 21 Some Features of High Density Interconnect Technology 7L

 

Figure 21 Some Features of High Density Interconnect Technology

At the time of writing this topic microvias of about 6mil in diameter were possible: the drilling operation is carried out prior to PCB lamination. Conventional through plated holes may be used with HDI technology.

The benefits of HDI for EMC performance are described in detail in Ref 1.

 

Fig 22 Shows both signal and return currents flow when a trace changes from one side of a reference plane to another through a via hole. Remember high speed / high frequency currents tend to flow in the region of conductor surfaces because of the skin effect.

Figure 22 An Example of current flow when changing layers for one side of the reference plane to the other 6T

 

 

Figure 22 An Example of current flow when changing layers for one side of the reference plane to the other

Fig 23 Illustrates the effect of physical discontinuities on current flow and hence on trace impedance discontinuities.

Figure 23 Examples of Trace Impedance Discontinuities

 

Figure 23 Examples of Trace Impedance Discontinuities

Fig 23 (a) shows the effect of holes in a trace. The holes cause the current flow to be restricted which increases the current density and cause the inductance near to the hole to increase. The resulting impedance discontinuity causes reflections at the holes which in turn produces em radiation. Clearly the smaller the holes the better and the best solution is to dispense with them.

Fig 23 (b) shows a sharp, 90 degree, change in trace direction, which results in an impedance discontinuity which cause reflections and radiation. Make trace changes in direction gradual and if possible eliminate them.

Fig 23 (c) shows a trace splitting into two. Too minimise impedance discontinuities the characteristic impedance of section X should half that of sections X and Y. Note that signal flow is not reversible for high speed signals, signal flow from right to left will cause severe degradation signal integrity and significant em radiation.

Fig 23 (d) shows a trace changing layers to avoid shorting with another trace. Impedance discontinuities occur at the vias but also because of the change in layers. The characteristic impedance of section 1 and section 3 is the same, but the deeper section, section 2, has a lower characteristic impedance because of the change in thickness of the dielectric above it and because of the change in relative permittivity from air/photo resist to PCB layer material.

To summarise the effects illustrated in Fig 23, make traces short, straight and confined to a single layers. Make via hole diameters as small as possible.

Fig 24 Illustrates some typical errors associated with antipads on PCBs; all the examples shown in the figures degrade the screening effect of PCB reference planes.

Figure 24 Examples of Antipad Merging Errors 4B

 

Figure 24 Examples of Antipad Merging Errors

Fig 25 shows an example of a single bidirectional interconnect that could be part of data bus on a PCB backplane. Only one transmitter can send data over the bus a time, to prevent bus contention.

All the bus interconnects must be terminated at both ends to prevent reflections, which increases power dissipation.

The output impedance of transmitters must be small in comparison with half the characteristic impedance of the line to ensure acceptable signal integrity.

Reflections and hence radiation occurs at every stub on the bus due to the mismatch in impedance caused by the input capacitance of the receiver gates.

Crosstalk is a problem because of the long length of the backplane interconnects and so is em radiation.

We should remember that the bus consists of a large number of interconnects, 8, 13, 32 etc and that these are driven synchronously.

Figure 25 An Example of a Bidirectional Bus on a PCB Backplane (based on 6S)

 

Figure 25 An Example of a Bidirectional Bus on a PCB Backplane

Fig 26 compares a conventional bus arrangement (26 a), with a data transfer arrangement based on low voltage differential signaling techniques (LVDS), (26 b).

Figure 26 Comparison of a Conventional Bus Arrangement and LVDS Bus Arrangement

 

Figure 26 Comparison of a Conventional Bus Arrangement and LVDS Bus Arrangement

The LVDS bus uses point to point unidirectional interconnects: parallel data is converted to serial data prior to its transmission and back to serial data after reception. Data transmission rates in excess of 1GHz are possible and both signal integrity and EMC performance are excellent.

It may be sensible to consider the LVDS techniques for transferring data over long lengths, even for modest system speeds. Note that bus contention is not possible and several links may be active at the same time.

The basic circuit arrangement arrangement of a LVDS interconnect is shown in Fig 27 (a). The output driver stage of the transmitter consists of 4 constant current sources connected as a bridge.

Figure 27 Basic Elements of a LVDS Interconnect

 

 

Figure 27 Basic Elements of a LVDS Interconnect

When S1 and S2 are on S3 and S4 are off, and current flow is as depicted in Fig 27 (a). This current flows along the differential transmission line and through the matching terminating impedance Z0. The voltage developed across this impedance is IZ0. Typically, I=3.5mA and Z0= 100 Ohm, which corresponds to a voltage across Z0 of +350mV, which we shall assume is a logic HI.

The comparator is a high speed analogue comparator with a high common mode rejection ratio. Consequently any common mode interference causes by incoming em radiation, which appears as a common mode signal on both traces of the differential transmission line, is rejected.

If S1 and S2 are turned off and S3 and S4 are turned on current flow along the interconnect is reversed which causes the voltage across Z0 to reverses, which is interpreted as a logic LO.

Current taken by the current mode driver circuit is almost constant for either logic state, which means disturbances on the power supply planes is minimal and decoupling is simplified.

Fig 27 (b) shows a fragment of the differential transmission line running over the PCB 0V reference plane. Electromagnetic radiation is small because of the close proximity of the traces carrying identical currents flowing in opposite directions.

Fig 28 shows an example of a shielded strip line: the signal reference planes are bonded together with two rows of vias, which form a shielding wall. The separation between the vias should be small in comparison with the shortest wavelength of interest

Figure 28 A Shielded Stripline on a PCB 6AL

 

 

 

Figure 28 A Shielded Stripline on a PCB

Fig 29 indicates how screening effectiveness is degraded by a single aperture of different dimensions. Remember that apertures in PCB reference planes degrade shielding effectiveness.

Figure 29 Estimate of Shielding Efficiency for a Single Aperture 2H

 

Figure 29 Estimate of Shielding Efficiency for a Single Aperture

Fig 30 shows a cross section of shielded PCB transmission line, using metalised trenches. This type of shield is very effective.

Figure 30 Cross-section of a Shielded Transmission Line 6AE

 

Figure 30 Cross-section of a Shielded Transmission Line

Fig 31 shows a cross section of a fully shielded PCB, that uses a variety of shielding methods. Note in particular the shielding of the I/O cable which has its shield (not shown) bonded to the connector shield over 360 degrees.

Figure 31 A Fully Shielded PCB 2S

 

Figure 31 A Fully Shielded PCB

Fig 32 shows a fully shielded PCB with a fully customised ASIC bonded to the PCB, using "Chip on Board" (COB) bonding techniques.

Figure 32 A Fully Shielded PC Busing an ASIC (COB) 8D

 

 

 

Figure 32 A Fully Shielded PC Busing an ASIC (COB)

Finally Fig 33 shows the partioning and screening of a cell phone which uses a metalised plastic case in conjunction with conductive gaskets.

Figure 33 An Example of a Cellphone

 

Figure 33 An Example of a Cellphone

 

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Useful Links

You may find the courseware at the following links useful:

 

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Topic Summary

In this topic we have covered:

 

The underpinning principles of PCB design techniques

 

The effects of high speed operation on EMC

 

Partitioning at product level

 

PCB layout & segregation

 

PCB Stackup European Standards relating to radiated emissions and susceptibility

 

PCB RF design techniques

 

Extensive use of diagrams have been uses and where appropriate spreadsheets.

 

Several useful links have been provided that may assist you when studying this topic.

 

The design techniques covered in this topic are illustrative, they are not meant to be exhaustive. However it is clear that both EMC and Signal integrity are intimately related and should be integral to the design process from the outset of product development.

 

 

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Updated:18:06:08 RJH

 

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