A 64 pin DIP will have 32 pins on each side, so be over 3 inches long, probably using a spacing between rows of 0.75 inch – a monstrous beast!
The alternatives unfortunately do not include the SOIC, where the range of standards only goes up to 28 leads. Even using the thin small outline package (TSOP), with leads on 0.5 mm pitch, the package is only available up to 56 pins.
However, the same gull-wing construction is available in the Quad Flat Pack, and this would have 16 leads on each four sides, probably on 0.8 mm pitch. A package of that type would have dimensions tip-to-tip of around 18 mm square.
Alternative packages include chip carriers. The standard pin spacing for both ceramic and plastic types is 1.27 mm. A few minutes’ web browsing will show you that 64-pin is not a standard, but 68-pin is, and the PLCC68 has overall dimensions 25 mm square. The Intel Packaging Handbook shows that a leadless chip carrier variant is available, but this is only about 1mm smaller, and substantially more expensive.
So far, the smaller QFP wins out, and gives a substantial improvement in size. To get more pins, one has to look at an area array, which uses the whole of the underside for connections, and not just the periphery. Again the PGA standard has 68 pins, on 0.1 inch spacing, and with two rows of pins around the die. The overall maximum dimension of the array is 30 mm, so is actually bigger than either surface mount option.
If there is a PGA product, then one might expect a Ball Grid Array to be smaller. This would be the case, except that arrays on standard 1.27 mm pitch don’t usually have so few leads. The smallest package, the 208-pin, has a footprint 23 mm across – again, not really an advantage, and certainly more complex to assemble and rework than a QFP.
There are many variants of µBGA packages at around this pin count, but it is surprising how many of these packages have slightly fewer than 64 leads – you would be well advised to check how many leads have actually been used, as this may enable you to specify a smaller package. Typically Chip Scale Packages, such as those from Tessera, will be less than 1mm bigger than the bare die. A typical package would be of the order of 9 mm square, but there are few standards in this area.
Of course, one could argue that a redesign is not needed if you are able to get the device in a 64 pin QFP, because adaptors are available. A Google search for “64-pin QFP” + dimensions yielded a lead to www.arieselec.com whose 64-304518-10 is an adaptor for using a 64-pin QFP in place of a 64 shrink DIP package!