Author: Jeff Ormerod
Detailed instructions for using individual CAD packages are provided in the appropriate walkthroughs. The following are general guidelines that will help ensure fast, responsive, reliable, trouble free operation. Pay particular attention to the ALWAYS and NEVER items. Each one of these relates to mistakes students have made in the past and in doing so have caused no end of problems!!
Almost all applications software requires a correctly defined directory structure for successful operation. ALWAYS organise your directory structure such that your home directory contains only sub-directories (i.e. no files), one for each of your various projects.
Typically a project will consist of a number of schematics, simulation files, configuration files etc. NEVER attempt to distribute these over a number of different directories by creating individual schematics, etc. for the same project in different project directories. Most CAD software will not enable you to combine them when required. NEVER put more than one project in the same directory, this will greatly confuse the CAD software and can lead to disaster.
The great majority of cases involving CAD screw ups result from invoking the software from the wrong project directory. ALWAYS move into the appropriate project directory before invoking the software and NEVER attempt to invoke the software from your home directory. With Cadence this sets up a complete environment in your home directory which conflicts with that already established in your project directories.
All applications software has a tendency to crash occasionally. Should this happen you will lose any work that you are currently creating or editing. Locate the "Save Design" option for the software you are using and ALWAYS use this frequently as your work proceeds.
If you are using CAD software remotely there will be a small latency in
the response of the system. The following are a number of suggestions for
achieving best performance.
|The design will not compile or simulate||The schematic and test vector file have different names to that of the project||Ensure that the project name is used for both the schematic and the test vector file|
|The compiler refers to signals not present in the schematic||The project name and schematic names are different||Set the schematic name to that of the project|
|The simulator refers to signals not present in the schematic||The schematic and the test vector file have different names||Set the test vector file name to that of the schematic|
|The simulation output does not change with a modified vector file||The simulation has been run with an scf file rather than a vec file||Remove the scf file name in the simulation form and replace with the vector file name|
|The simulation output displays signals as indeterminate values||The vector file has not been translated, compiled or simulated||Select the start button 3 times on the simulation run form to implement the translation/compilation and simulation.|
|Command Interpreter Window reports errors with libraries, cellnames, processes etc. on an existing design when Cadence is invoked||Corrupt cds.lib file
Spurious cds.lib file in the home directory
Corrupt .cdsenv file in the home directory
|Exit from Cadence, remove the cds.lib file from
the project directory and restart Cadence
Exit from Cadence, delete the cds.lib file from the home directory and restart Cadence
Exit from Cadence, delete the .cdsenv file from the home directory and restart Cadence
|A project library has disappeared from the library list when attempting to open an existing design||Incomplete cds.lib file||Create a new project library with the same name as the existing one|
|Schematic display degrades when entering components||No automatic refresh||Use the Redraw option or function key f6 to refresh the screen|
|Verilog simulation output does not follow the specified test patterns||The testfixture.verilog file has been used for the test patterns||Copy the testfixture.verilog file to the testfixture.new file and add the test patterns|
|Verilog simulator will not run||Corrupt run directory||Delete the run directory (cellname.run1) and restart Verilog|
|Verilog simulation displays large quantities of timing information||Capacitance values are being displayed for every component in the design||Remove the +dlverbose option from the Verilog Setup form|
|Leapfrog libraries (std and IEEE) not present in the library list||Corrupt cds.lib file in project directory
Spurious cds.lib file in the home directory
|Exit from Leapfrog, delete the cds.lib
file from the project directory and restart Leapfrog.
Exit from Leapfrog, delete the cds.lib file from the home directory and restart Leapfrog.
|VHDL source files will not compile. Error messages displayed relating to the work library||Work library not selected||Activate the work library box on the Compile VHDL Design form|
Updated 11.10.05 RA