Project Information

If this project is available and you wish to be considered for it, please email the proposer. There is no automatic form for this action and the allocation process is likely to take several days. If you have not heard within a week, please email the Postgraduate Programmes Office on ami@bolton.ac.uk

 
Project Reference: 53 
Title DC-DC Synchronous Buck Controller  
Project Status: completed  
 
Proposer's Name: Daragh MacGabhann 
Company/University: Maxim Integrated Products 
Phone: +1-919-605-7172 
Email: Daragh_MacGabhann@ieee.or 
Proposal Date: 10/10/2005 
Brief description
Modern day and future microprocessors and their associated systems require specialised power management systems to ensure correct operation. Once such topology is a Buck controller, the controller effectively converts a high voltage with low current to a low voltage with high current. A synchronous buck controller involves having a considerable understanding of Analog IC design and control theory. This project would allow me to obtain such knowledge and would involve the research and design of blocks such as bandgaps, amplifiers, oscillators and combining them into a complete system to produce an IC that would be a synchronous buck controller. The project would involve the study of control theory and analog IC design with simulations performed to verify the blocks and the completed system.  
Project outcomes
ASIC to be fabricated No 
Hardware to be produced No  
Software to be produced Yes  
Requirements
Dedicated hardware that will be essential for the project. None 
Specialist software that will be essential for the project. Access to an analog simulator along with accociated models for the MOS, BJT, Caps, and resistors. An example of such would be HSPICE or PSPICE. Having completed several modules invloving analog simulation I feel the analog simulator available on the M.Sc server is adequate. 
Staff comments
Daragh indicates a planned start date of 10/07/06, dependent on work commitments. Neil  

form and database created by cf1
layout updated 30 Jan 08 RA